tilelink2: support ready-valid enqueue+dequeue on register fields
This commit is contained in:
Wesley W. Terpstra
parent
77cf186cf0
commit
967d8f108c
@ -4,38 +4,214 @@ package uncore.tilelink2
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import Chisel._
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import Chisel._
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case class RegField(width: Int, read: RegField.ReadFn, write: RegField.WriteFn)
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case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt))
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object RegReadFn
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{
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// (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt)
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// iready may combinationally depend on oready
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// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
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// effects must become visible only on the cycle after ovalid && oready
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implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) =
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new RegReadFn(false, x)
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// (ofire: Bool) => (data: UInt)
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// effects must become visible on the cycle after ofire
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implicit def apply(x: Bool => UInt) =
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new RegReadFn(true, { case (_, oready) =>
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(Bool(true), Bool(true), x(oready))
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})
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// read from a register
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implicit def apply(x: UInt) =
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new RegReadFn(true, { case (_, _) =>
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(Bool(true), Bool(true), x)
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})
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// noop
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implicit def apply(x: Unit) =
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new RegReadFn(true, { case (_, _) =>
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(Bool(true), Bool(true), UInt(0))
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})
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}
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case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool))
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object RegWriteFn
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{
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// (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool)
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// iready may combinationally depend on both oready and data
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// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
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// effects must become visible only on the cycle after ovalid && oready
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implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) =
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new RegWriteFn(false, x)
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// (ofire: Bool, data: UInt) => ()
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// effects must become visible on the cycle after ofire
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implicit def apply(x: (Bool, UInt) => Unit) =
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new RegWriteFn(true, { case (_, oready, data) =>
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x(oready, data)
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(Bool(true), Bool(true))
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})
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// updates a register
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implicit def apply(x: UInt) =
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new RegWriteFn(true, { case (_, oready, data) =>
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when (oready) { x := data }
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(Bool(true), Bool(true))
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})
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// noop
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implicit def apply(x: Unit) =
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new RegWriteFn(true, { case (_, _, _) =>
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(Bool(true), Bool(true))
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})
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}
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case class RegField(width: Int, read: RegReadFn, write: RegWriteFn)
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{
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{
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require (width > 0)
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require (width > 0)
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def pipelined = !read.combinational || !write.combinational
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}
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}
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object RegField
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object RegField
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{
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{
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type ReadFn = Bool => (Bool, UInt)
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type WriteFn = (Bool, UInt) => Bool
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type Map = (Int, Seq[RegField])
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type Map = (Int, Seq[RegField])
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def apply(n: Int) : RegField = apply(n, (), ())
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def apply(n: Int) : RegField = apply(n, noR, noW)
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def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw)
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def apply(n: Int, rw: UInt) : RegField = apply(n, regR(rw), regW(rw))
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def R(n: Int, r: RegReadFn) : RegField = apply(n, r, ())
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def apply(n: Int, r: UInt, w: UInt) : RegField = apply(n, regR(r), regW(w))
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def W(n: Int, w: RegWriteFn) : RegField = apply(n, (), w)
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def apply(n: Int, r: UInt, w: WriteFn) : RegField = apply(n, regR(r), w)
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def apply(n: Int, r: ReadFn, w: UInt) : RegField = apply(n, r, regW(w))
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def R(n: Int, r: ReadFn) : RegField = apply(n, r, noW)
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def R(n: Int, r: UInt) : RegField = R(n, regR(r))
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def W(n: Int, w: WriteFn) : RegField = apply(n, noR, w)
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def W(n: Int, w: UInt) : RegField = W(n, regW(w))
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private val noR = (en: Bool) => (Bool(true), UInt(0))
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private val noW = (en: Bool, in: UInt) => Bool(true)
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private def regR(reg: UInt) = (en: Bool) => (Bool(true), reg)
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private def regW(reg: UInt) = (en: Bool, in: UInt) =>
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{
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when (en) { reg := in }
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Bool(true)
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}
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}
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}
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trait HasRegMap
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trait HasRegMap
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{
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{
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def regmap(mapping: RegField.Map*): Unit
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def regmap(mapping: RegField.Map*): Unit
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}
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}
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case class RegFieldParams(indexBits: Int, maskBits: Int, extraBits: Int)
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class RegFieldInput(params: RegFieldParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val index = UInt(width = params.indexBits)
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val data = UInt(width = params.maskBits*8)
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val mask = UInt(width = params.maskBits)
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val extra = UInt(width = params.extraBits)
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}
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class RegFieldOutput(params: RegFieldParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val data = UInt(width = params.maskBits*8)
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val extra = UInt(width = params.extraBits)
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}
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object RegFieldHelper
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{
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// Create a generic register-based device
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def apply(bytes: Int, concurrency: Option[Int], in: DecoupledIO[RegFieldInput], mapping: RegField.Map*) = {
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val regmap = mapping.toList
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require (!regmap.isEmpty)
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// Flatten the regmap into (Reg:Int, Offset:Int, field:RegField)
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val flat = regmap.map { case (reg, fields) =>
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val offsets = fields.scanLeft(0)(_ + _.width).init
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(offsets zip fields) map { case (o, f) => (reg, o, f) }
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}.flatten
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require (!flat.isEmpty)
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val endIndex = 1 << log2Ceil(regmap.map(_._1).max+1)
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val params = RegFieldParams(log2Up(endIndex), bytes, in.bits.params.extraBits)
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val out = Wire(Decoupled(new RegFieldOutput(params)))
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val front = Wire(Decoupled(new RegFieldInput(params)))
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front.bits := in.bits
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// Must this device pipeline the control channel?
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val pipelined = flat.map(_._3.pipelined).reduce(_ || _)
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val depth = concurrency.getOrElse(if (pipelined) 1 else 0)
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require (depth >= 0)
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require (!pipelined || depth > 0)
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val back = if (depth > 0) Queue(front, depth, pipe = depth == 1) else front
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// Forward declaration of all flow control signals
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val rivalid = Wire(Vec(flat.size, Bool()))
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val wivalid = Wire(Vec(flat.size, Bool()))
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val riready = Wire(Vec(flat.size, Bool()))
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val wiready = Wire(Vec(flat.size, Bool()))
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val rovalid = Wire(Vec(flat.size, Bool()))
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val wovalid = Wire(Vec(flat.size, Bool()))
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val roready = Wire(Vec(flat.size, Bool()))
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val woready = Wire(Vec(flat.size, Bool()))
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// Per-register list of all control signals needed for data to flow
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val rifire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val wifire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val rofire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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val wofire = Array.tabulate(endIndex) { i => Seq(Bool(true)) }
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// The output values for each register
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val dataOut = Array.tabulate(endIndex) { _ => UInt(0) }
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// Which bits are touched?
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val frontMask = FillInterleaved(8, front.bits.mask)
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val backMask = FillInterleaved(8, back .bits.mask)
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// Connect the fields
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for (i <- 0 until flat.size) {
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val (reg, low, field) = flat(i)
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val high = low + field.width - 1
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// Confirm that no register is too big
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require (high <= 8*bytes)
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val rimask = frontMask(high, low).orR()
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val wimask = frontMask(high, low).andR()
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val romask = backMask(high, low).orR()
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val womask = backMask(high, low).andR()
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val data = if (field.write.combinational) back.bits.data else front.bits.data
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val (f_riready, f_rovalid, f_data) = field.read.fn(rivalid(i) && rimask, roready(i) && romask)
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val (f_wiready, f_wovalid) = field.write.fn(wivalid(i) && wimask, woready(i) && womask, data)
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riready(i) := f_riready || !rimask
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wiready(i) := f_wiready || !wimask
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rovalid(i) := f_rovalid || !romask
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wovalid(i) := f_wovalid || !womask
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rifire(reg) = riready(i) +: rifire(reg)
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wifire(reg) = wiready(i) +: wifire(reg)
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rofire(reg) = rovalid(i) +: rofire(reg)
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wofire(reg) = wovalid(i) +: wofire(reg)
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dataOut(reg) = dataOut(reg) | (f_data << low)
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}
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// Is the selected register ready?
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val rifireMux = Vec(rifire.map(_.reduce(_ && _)))
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val wifireMux = Vec(wifire.map(_.reduce(_ && _)))
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val rofireMux = Vec(rofire.map(_.reduce(_ && _)))
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val wofireMux = Vec(wofire.map(_.reduce(_ && _)))
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val iready = Mux(front.bits.read, rifireMux(front.bits.index), wifireMux(front.bits.index))
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val oready = Mux(back .bits.read, rofireMux(back .bits.index), wofireMux(back .bits.index))
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// Connect the pipeline
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in.ready := front.ready && iready
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front.valid := in.valid && iready
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back.ready := out.ready && oready
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out.valid := back.valid && oready
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// Which register is touched?
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val frontSel = UIntToOH(front.bits.index)
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val backSel = UIntToOH(back.bits.index)
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// Include the per-register one-hot selected criteria
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for (reg <- 0 until endIndex) {
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rifire(reg) = (in.valid && front.ready && front.bits.read && frontSel(reg)) +: rifire(reg)
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wifire(reg) = (in.valid && front.ready && !front.bits.read && frontSel(reg)) +: wifire(reg)
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rofire(reg) = (back.valid && out.ready && back .bits.read && backSel (reg)) +: rofire(reg)
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wofire(reg) = (back.valid && out.ready && !back .bits.read && backSel (reg)) +: wofire(reg)
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}
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// Connect the field's ivalid and oready
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for (i <- 0 until flat.size) {
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val (reg, _, _ ) = flat(i)
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rivalid(i) := rifire(reg).filter(_ ne riready(i)).reduce(_ && _)
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wivalid(i) := wifire(reg).filter(_ ne wiready(i)).reduce(_ && _)
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roready(i) := rofire(reg).filter(_ ne rovalid(i)).reduce(_ && _)
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woready(i) := wofire(reg).filter(_ ne wovalid(i)).reduce(_ && _)
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}
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out.bits.read := back.bits.read
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out.bits.data := Vec(dataOut)(back.bits.index)
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out.bits.extra := back.bits.extra
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(endIndex, out)
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}
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}
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@ -4,7 +4,7 @@ package uncore.tilelink2
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import Chisel._
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import Chisel._
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class TLRegisterNode(address: AddressSet, beatBytes: Int = 4)
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class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatBytes: Int = 4)
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extends TLManagerNode(beatBytes, TLManagerParameters(
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extends TLManagerNode(beatBytes, TLManagerParameters(
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address = Seq(address),
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address = Seq(address),
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supportsGet = TransferSizes(1, beatBytes),
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supportsGet = TransferSizes(1, beatBytes),
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@ -17,87 +17,51 @@ class TLRegisterNode(address: AddressSet, beatBytes: Int = 4)
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// Calling this method causes the matching TL2 bundle to be
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// Calling this method causes the matching TL2 bundle to be
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// configured to route all requests to the listed RegFields.
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// configured to route all requests to the listed RegFields.
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def regmap(mapping: RegField.Map*) = {
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def regmap(mapping: RegField.Map*) = {
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val regmap = mapping.toList
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val a = bundleIn(0).a
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require (!regmap.isEmpty)
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val d = bundleIn(0).d
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val edge = edgesIn(0)
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// Flatten the regmap into (Reg:Int, Offset:Int, field:RegField)
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val params = RegFieldParams(log2Up(address.mask+1), beatBytes, edge.bundle.sourceBits + edge.bundle.sizeBits)
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val flat = regmap.map { case (reg, fields) =>
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val in = Wire(Decoupled(new RegFieldInput(params)))
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val offsets = fields.scanLeft(0)(_ + _.width).init
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in.bits.read := a.bits.opcode === TLMessages.Get
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(offsets zip fields) map { case (o, f) => (reg, o, f) }
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in.bits.index := a.bits.address >> log2Ceil(beatBytes)
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}.flatten
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in.bits.data := a.bits.data
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in.bits.mask := a.bits.wmask
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in.bits.extra := Cat(a.bits.source, a.bits.size)
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// Confirm that no register is too big
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// Invoke the register map builder
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require (flat.map(_._2).max <= beatBytes*8)
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val (endIndex, out) = RegFieldHelper(beatBytes, concurrency, in, mapping:_*)
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// All registers must fit inside the device address space
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// All registers must fit inside the device address space
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val maxIndex = regmap.map(_._1).max
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require (address.mask >= (endIndex-1)*beatBytes)
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require (address.mask >= maxIndex*beatBytes)
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// Which register is touched?
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// No flow control needed
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val alignBits = log2Ceil(beatBytes)
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in.valid := a.valid
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val addressBits = log2Up(maxIndex+1)
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a.ready := in.ready
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val a = bundleIn(0).a // Must apply Queue !!! (so no change once started)
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d.valid := out.valid
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val d = bundleIn(0).d
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out.ready := d.ready
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val regIdx = a.bits.address(addressBits+alignBits-1, alignBits)
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val regSel = UIntToOH(regIdx)
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// What is the access?
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val sizeBits = edge.bundle.sizeBits
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val opcode = a.bits.opcode
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d.bits := edge.AccessAck(out.bits.extra >> sizeBits, out.bits.extra(sizeBits-1, 0))
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val read = a.valid && opcode === TLMessages.Get
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val write = a.valid && (opcode === TLMessages.PutFullData || opcode === TLMessages.PutPartialData)
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val wmaskWide = Vec.tabulate(beatBytes*8) { i => a.bits.wmask(i/8) } .toBits.asUInt
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val dataIn = a.bits.data & wmaskWide // zero undefined bits
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// The output values for each register
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val dataOutAcc = Array.tabulate(maxIndex+1) { _ => UInt(0) }
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// The ready state for read and write
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val rReadyAcc = Array.tabulate(maxIndex+1) { _ => Bool(true) }
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val wReadyAcc = Array.tabulate(maxIndex+1) { _ => Bool(true) }
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// Apply all the field methods
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flat.foreach { case (reg, low, field) =>
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val high = low + field.width - 1
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val rfire = wmaskWide(high, low).orR()
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val wfire = wmaskWide(high, low).andR()
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val sel = regSel(reg)
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val ren = read && sel && rfire
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val wen = write && sel && wfire
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val (rReady, rResult) = field.read(ren)
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val wReady = field.write(wen, dataIn(high, low))
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dataOutAcc(reg) = dataOutAcc(reg) | (rResult << low)
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rReadyAcc(reg) = rReadyAcc(reg) && (!rfire || rReady)
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wReadyAcc(reg) = wReadyAcc(reg) && (!wfire || wReady)
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}
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// Create the output data signal
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val dataOut = Vec(dataOutAcc)(regIdx)
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val rReady = Vec(rReadyAcc)(regIdx)
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val wReady = Vec(wReadyAcc)(regIdx)
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||||||
|
|
||||||
val ready = (read && rReady) || (write && wReady)
|
|
||||||
a.ready := ready && d.ready
|
|
||||||
d.valid := a.valid && ready
|
|
||||||
|
|
||||||
val edge = edgesIn(0)
|
|
||||||
d.bits := edge.AccessAck(a.bits.source, a.bits.size)
|
|
||||||
// avoid a Mux on the data bus by manually overriding two fields
|
// avoid a Mux on the data bus by manually overriding two fields
|
||||||
d.bits.data := dataOut
|
d.bits.data := out.bits.data
|
||||||
d.bits.opcode := Mux(opcode === TLMessages.Get, TLMessages.AccessAck, TLMessages.AccessAckData)
|
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
object TLRegisterNode
|
object TLRegisterNode
|
||||||
{
|
{
|
||||||
def apply(address: AddressSet, beatBytes: Int = 4) = new TLRegisterNode(address, beatBytes)
|
def apply(address: AddressSet, concurrency: Option[Int] = None, beatBytes: Int = 4) =
|
||||||
|
new TLRegisterNode(address, concurrency, beatBytes)
|
||||||
}
|
}
|
||||||
|
|
||||||
// These convenience methods below combine to make it possible to create a TL2
|
// These convenience methods below combine to make it possible to create a TL2
|
||||||
// register mapped device from a totally abstract register mapped device.
|
// register mapped device from a totally abstract register mapped device.
|
||||||
// See GPIO.scala in this directory for an example
|
// See GPIO.scala in this directory for an example
|
||||||
|
|
||||||
abstract class TLRegFactory(address: AddressSet, beatBytes: Int) extends TLFactory
|
abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLFactory
|
||||||
{
|
{
|
||||||
val node = TLRegisterNode(address, beatBytes)
|
val node = TLRegisterNode(address, concurrency, beatBytes)
|
||||||
}
|
}
|
||||||
|
|
||||||
class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle
|
class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle
|
||||||
@ -110,10 +74,10 @@ class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: T
|
|||||||
}
|
}
|
||||||
|
|
||||||
class TLRegisterRouter[B <: Bundle, M <: TLModule]
|
class TLRegisterRouter[B <: Bundle, M <: TLModule]
|
||||||
(address: Option[BigInt] = None, size: BigInt = 4096, beatBytes: Int = 4)
|
(address: Option[BigInt] = None, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
|
||||||
(bundleBuilder: Vec[TLBundle] => B)
|
(bundleBuilder: Vec[TLBundle] => B)
|
||||||
(moduleBuilder: (=> B, TLRegFactory) => M)
|
(moduleBuilder: (=> B, TLRegFactory) => M)
|
||||||
extends TLRegFactory(AddressSet(size-1, address), beatBytes)
|
extends TLRegFactory(AddressSet(size-1, address), concurrency, beatBytes)
|
||||||
{
|
{
|
||||||
require (size % 4096 == 0) // devices should be 4K aligned
|
require (size % 4096 == 0) // devices should be 4K aligned
|
||||||
require (isPow2(size))
|
require (isPow2(size))
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user