riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tighten an assert condition

Browse Source 
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
This commit is contained in:
Andrew Waterman 2016-09-12 12:01:04 -07:00
parent beb141a20b
commit 96185e4b16
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/rocket.scala
View File

@ -632,7 +632,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
io.dmem.invalidate_lr := wb_xcpt io.dmem.invalidate_lr := wb_xcpt
io.dmem.s1_data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) io.dmem.s1_data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
io.dmem.s1_kill := killm_common || mem_breakpoint io.dmem.s1_kill := killm_common || mem_breakpoint
when (mem_xcpt && !io.dmem.s1_kill) { when (mem_ctrl.mem && mem_xcpt && !io.dmem.s1_kill) {
assert(io.dmem.xcpt.asUInt.orR) // make sure s1_kill is exhaustive assert(io.dmem.xcpt.asUInt.orR) // make sure s1_kill is exhaustive
} }