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Merge pull request #291 from ucb-bar/move-bootrom

Move BootROM from Coreplex to Periphery
This commit is contained in:
Yunsup Lee 2016-09-14 19:51:16 -07:00 committed by GitHub
commit 96110caca1
5 changed files with 53 additions and 33 deletions

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@ -11,8 +11,6 @@ import uncore.util._
import uncore.converters._ import uncore.converters._
import rocket._ import rocket._
import rocket.Util._ import rocket.Util._
import java.nio.{ByteBuffer,ByteOrder}
import java.nio.file.{Files, Paths}
/** Number of memory channels */ /** Number of memory channels */
case object NMemoryChannels extends Field[Int] case object NMemoryChannels extends Field[Int]
@ -34,7 +32,6 @@ trait HasCoreplexParameters {
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" }) lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" }) lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" }) lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
lazy val configString = p(rocketchip.ConfigString).get
lazy val globalAddrMap = p(rocketchip.GlobalAddrMap).get lazy val globalAddrMap = p(rocketchip.GlobalAddrMap).get
} }
@ -130,28 +127,6 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
p.alterPartial({case TLId => "L2toMMIO"})) p.alterPartial({case TLId => "L2toMMIO"}))
} }
def makeBootROM()(implicit p: Parameters) = {
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata)
rom.order(ByteOrder.LITTLE_ENDIAN)
// for now, have the reset vector jump straight to memory
val memBase = (
if (globalAddrMap contains "mem") globalAddrMap("mem")
else globalAddrMap("io:int:dmem0")
).start
val resetToMemDist = memBase - p(ResetVector)
require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
val configStringAddr = p(ResetVector).toInt + rom.capacity
require(rom.getInt(12) == 0,
"Config string address position should not be occupied by code")
rom.putInt(12, configStringAddr)
rom.array() ++ (configString.getBytes.toSeq)
}
def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = { def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
val ioAddrMap = globalAddrMap.subMap("io") val ioAddrMap = globalAddrMap.subMap("io")
@ -184,9 +159,6 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
for ((t, m) <- (tileList.map(_.io.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _))) for ((t, m) <- (tileList.map(_.io.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _)))
t <> ClientUncachedTileLinkEnqueuer(m, 1) t <> ClientUncachedTileLinkEnqueuer(m, 1)
val bootROM = Module(new ROMSlave(makeBootROM()))
bootROM.io <> mmioNetwork.port("int:bootrom")
io.master.mmio.foreach { _ <> mmioNetwork.port("ext") } io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
} }
} }

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@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true) io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("io:int:bootrom").start) io.cache.req.bits.addr := UInt(addrMap("io:ext:bootrom").start)
io.cache.req.bits.typ := UInt(log2Ceil(32 / 8)) io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
io.cache.req.bits.cmd := M_XRD io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0) io.cache.req.bits.tag := UInt(0)

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@ -303,6 +303,29 @@ trait PeripheryAONModule extends HasPeripheryParameters {
///// /////
trait PeripheryBootROM extends LazyModule {
implicit val p: Parameters
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("bootrom", MemRange(0x1000, 4096, MemAttr(AddrMapProt.RX))))
}
trait PeripheryBootROMBundle {
implicit val p: Parameters
}
trait PeripheryBootROMModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryBootROM
val io: PeripheryBootROMBundle
val mmioNetwork: Option[TileLinkRecursiveInterconnect]
val bootROM = Module(new ROMSlave(GenerateBootROM(p))(innerMMIOParams))
bootROM.io <> mmioNetwork.get.port("bootrom")
}
/////
trait PeripheryTestRAM extends LazyModule { trait PeripheryTestRAM extends LazyModule {
implicit val p: Parameters implicit val p: Parameters
val pDevices: ResourceManager[AddrMapEntry] val pDevices: ResourceManager[AddrMapEntry]

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@ -75,17 +75,17 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
/** Example Top with Periphery */ /** Example Top with Periphery */
class ExampleTop(p: Parameters) extends BaseTop(p) class ExampleTop(p: Parameters) extends BaseTop(p)
with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave { with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _))) override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
} }
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c) class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b) class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
/** Example Top with TestRAM */ /** Example Top with TestRAM */

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@ -9,6 +9,9 @@ import rocket._
import rocket.Util._ import rocket.Util._
import coreplex._ import coreplex._
import java.nio.file.{Files, Paths}
import java.nio.{ByteBuffer, ByteOrder}
class RangeManager { class RangeManager {
private var finalized = false private var finalized = false
private val l = collection.mutable.HashMap[String, Int]() private val l = collection.mutable.HashMap[String, Int]()
@ -52,7 +55,6 @@ object GenerateGlobalAddrMap {
lazy val intIOAddrMap: AddrMap = { lazy val intIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]() val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX))) entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW))) entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
require(p(NTiles) == 1) // TODO relax this require(p(NTiles) == 1) // TODO relax this
@ -146,3 +148,26 @@ object GenerateConfigString {
res.toString res.toString
} }
} }
object GenerateBootROM {
def apply(p: Parameters) = {
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata)
rom.order(ByteOrder.LITTLE_ENDIAN)
// for now, have the reset vector jump straight to memory
val memBase = (
if (p(GlobalAddrMap).get contains "mem") p(GlobalAddrMap).get("mem")
else p(GlobalAddrMap).get("io:int:dmem0")
).start
val resetToMemDist = memBase - p(ResetVector)
require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
val configStringAddr = p(ResetVector).toInt + rom.capacity
require(rom.getInt(12) == 0,
"Config string address position should not be occupied by code")
rom.putInt(12, configStringAddr)
rom.array() ++ (p(ConfigString).get.getBytes.toSeq)
}
}