From f5729c9f2554f2470be3aa8877e57f1de24365e8 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 28 Jan 2013 16:44:17 -0800 Subject: [PATCH 1/5] removed ack_required field from grant messages --- rocket/src/main/scala/htif.scala | 2 +- rocket/src/main/scala/icache.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 611beb68..85c6bb50 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -109,7 +109,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo when (io.mem.grant.valid) { mem_acked := Bool(true) mem_gxid := io.mem.grant.bits.payload.master_xact_id - mem_needs_ack := io.mem.grant.bits.payload.require_ack + mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload) } io.mem.grant.ready := Bool(true) when (io.mem.abort.valid) { mem_nacked := Bool(true) } diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 5914daac..77ac7f9b 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -238,7 +238,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout) val finish_q = (new Queue(1)) { new GrantAck } - finish_q.io.enq.valid := refill_done && io.mem.grant.bits.payload.require_ack + finish_q.io.enq.valid := refill_done && c.co.requiresAck(io.mem.grant.bits.payload) finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id // output signals From e0361840bd455c9c83b4cc71a0e6317e11a7f187 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 28 Feb 2013 18:11:40 -0800 Subject: [PATCH 2/5] writebacks on release network pass asm tests and bmarks --- rocket/src/main/scala/arbiter.scala | 22 ++-- rocket/src/main/scala/icache.scala | 5 +- rocket/src/main/scala/nbdcache.scala | 148 ++++++++++++++++++--------- rocket/src/main/scala/tile.scala | 8 +- 4 files changed, 120 insertions(+), 63 deletions(-) diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index 3dc2f44e..4b8529e6 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -61,29 +61,29 @@ class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Com val requestor = Vec(n) { new UncachedRequestorIO }.flip } - var xi_bits = new Acquire - xi_bits := io.requestor(n-1).acquire.bits.payload - xi_bits.client_xact_id := Cat(io.requestor(n-1).acquire.bits.payload.client_xact_id, UFix(n-1, log2Up(n))) + var acq_bits = new Acquire + acq_bits := io.requestor(n-1).acquire.bits.payload + acq_bits.client_xact_id := Cat(io.requestor(n-1).acquire.bits.payload.client_xact_id, UFix(n-1, log2Up(n))) for (i <- n-2 to 0 by -1) { - var my_xi_bits = new Acquire - my_xi_bits := io.requestor(i).acquire.bits.payload - my_xi_bits.client_xact_id := Cat(io.requestor(i).acquire.bits.payload.client_xact_id, UFix(i, log2Up(n))) + var my_acq_bits = new Acquire + my_acq_bits := io.requestor(i).acquire.bits.payload + my_acq_bits.client_xact_id := Cat(io.requestor(i).acquire.bits.payload.client_xact_id, UFix(i, log2Up(n))) - xi_bits = Mux(io.requestor(i).acquire.valid, my_xi_bits, xi_bits) + acq_bits = Mux(io.requestor(i).acquire.valid, my_acq_bits, acq_bits) } - io.mem.acquire.bits.payload := xi_bits + io.mem.acquire.bits.payload := acq_bits io.mem.acquire.valid := io.requestor.map(_.acquire.valid).reduce(_||_) io.requestor(0).acquire.ready := io.mem.acquire.ready for (i <- 1 until n) io.requestor(i).acquire.ready := io.requestor(i-1).acquire.ready && !io.requestor(i-1).acquire.valid - var xf_bits = io.requestor(n-1).grant_ack.bits + var ga_bits = io.requestor(n-1).grant_ack.bits for (i <- n-2 to 0 by -1) - xf_bits = Mux(io.requestor(i).grant_ack.valid, io.requestor(i).grant_ack.bits, xf_bits) + ga_bits = Mux(io.requestor(i).grant_ack.valid, io.requestor(i).grant_ack.bits, ga_bits) - io.mem.grant_ack.bits := xf_bits + io.mem.grant_ack.bits := ga_bits io.mem.grant_ack.valid := io.requestor.map(_.grant_ack.valid).reduce(_||_) io.requestor(0).grant_ack.ready := io.mem.grant_ack.ready for (i <- 1 until n) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 77ac7f9b..764ba9ee 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -172,7 +172,8 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte val s2_miss = s2_valid && !s2_any_tag_hit rdy := state === s_ready && !s2_miss - val (rf_cnt, refill_done) = Counter(io.mem.grant.valid, REFILL_CYCLES) + Assert(!c.co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.") + val (rf_cnt, refill_done) = Counter(io.mem.grant.valid && !c.co.isVoluntary(io.mem.grant.bits.payload), REFILL_CYCLES) val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0) val enc_tagbits = c.code.width(c.tagbits) @@ -223,7 +224,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte for (i <- 0 until c.assoc) { val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) } val s1_dout = Reg(){ Bits() } - when (io.mem.grant.valid && repl_way === UFix(i)) { + when (io.mem.grant.valid && c.co.messageHasData(io.mem.grant.bits.payload) && repl_way === UFix(i)) { val d = io.mem.grant.bits.payload.data data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d) } diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index c0eac3ab..88adc3be 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -123,11 +123,18 @@ class DataWriteReq(implicit conf: DCacheConfig) extends Bundle { override def clone = new DataWriteReq().asInstanceOf[this.type] } +class InternalProbe(implicit conf: DCacheConfig) extends Probe { + val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) + + override def clone = new InternalProbe().asInstanceOf[this.type] +} + class WritebackReq(implicit conf: DCacheConfig) extends Bundle { val tag = Bits(width = conf.tagbits) val idx = Bits(width = conf.idxbits) val way_en = Bits(width = conf.ways) val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) + val r_type = UFix(width = RELEASE_TYPE_MAX_BITS) override def clone = new WritebackReq().asInstanceOf[this.type] } @@ -162,8 +169,9 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val req_bits = new MSHRReq().asInput val req_sdq_id = UFix(INPUT, log2Up(conf.nsdq)) - val idx_match = Bool(OUTPUT) - val tag = Bits(OUTPUT, conf.tagbits) + val idx_match = Bool(OUTPUT) + val probe_idx_match = Bool(OUTPUT) + val tag = Bits(OUTPUT, conf.tagbits) val mem_req = (new FIFOIO) { new Acquire } val mem_resp = new DataWriteReq().asOutput @@ -172,6 +180,9 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val replay = (new FIFOIO) { new Replay() } val mem_abort = (new PipeIO) { new Abort }.flip val mem_rep = (new PipeIO) { new Grant }.flip + val mem_probe = (new PipeIO) { new Probe }.flip + val mem_probe_ready = Bool(OUTPUT) + val self_probe = (new FIFOIO) { new InternalProbe } val mem_finish = (new FIFOIO) { new GrantAck } val wb_req = (new FIFOIO) { new WritebackReq } val probe_writeback = (new FIFOIO) { Bool() }.flip @@ -181,29 +192,45 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) { UFix() } val state = Reg(resetVal = s_invalid) - val acq_type = Reg { UFix() } + val acquire_type = Reg { UFix() } + val release_type = Reg { UFix() } val line_state = Reg { UFix() } val refill_count = Reg { UFix(width = log2Up(REFILL_CYCLES)) } val req = Reg { new MSHRReq() } + val sent_wb_req = Reg { Bool() } val req_cmd = io.req_bits.cmd val req_idx = req.addr(conf.untagbits-1,conf.offbits) val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits) + val probe_idx_match = req_idx === io.mem_probe.bits.addr(conf.untagbits-1,conf.offbits) val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits)) + val abort = io.mem_abort.valid && io.mem_abort.bits.client_xact_id === UFix(id) + val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id) + val refill_done = reply && refill_count.andR + val wb_done = reply && (state === s_wb_resp) + + val probe_wb_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.old_meta.tag + val probe_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.addr >> conf.untagbits + val handle_probe = (state != s_invalid) && probe_idx_match + val kill_probe = sent_wb_req && probe_wb_tag_match && conf.co.pendingVoluntaryReleaseIsSufficient(release_type, io.mem_probe.bits.p_type) + val probe_q = (new Queue(1, pipe = true, flow = true)) { new Probe } + probe_q.io.enq.valid := io.mem_probe.valid && handle_probe && sent_wb_req && !kill_probe + io.mem_probe_ready := probe_q.io.enq.ready && handle_probe + probe_q.io.enq.bits := io.mem_probe.bits + io.self_probe.valid := probe_q.io.deq.valid && (state != s_wb_resp) + probe_q.io.deq.ready := io.self_probe.ready && (state != s_wb_resp) + io.self_probe.bits := probe_q.io.deq.bits + io.self_probe.bits.client_xact_id := UFix(id) + val rpq = (new Queue(conf.nrpq)) { new Replay } rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(req_cmd) rpq.io.enq.bits := io.req_bits rpq.io.enq.bits.sdq_id := io.req_sdq_id rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid - val abort = io.mem_abort.valid && io.mem_abort.bits.client_xact_id === UFix(id) - val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id) - val refill_done = reply && refill_count.andR - val wb_done = reply && (state === s_wb_resp) - val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck } - finish_q.io.enq.valid := wb_done || refill_done + finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_rep.bits) finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id io.wb_req.valid := Bool(false) @@ -241,17 +268,22 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { when (io.probe_writeback.valid && idx_match) { io.wb_req.valid := Bool(false) when (io.probe_writeback.bits) { state := s_refill_req } - }.elsewhen (io.wb_req.ready) { state := s_wb_resp } + }.elsewhen (io.wb_req.ready) { + sent_wb_req := Bool(true) + state := s_wb_resp + } } when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req - acq_type := conf.co.getAcquireTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits) + acquire_type := conf.co.getAcquireTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits) } when ((state === s_invalid) && io.req_pri_val) { line_state := conf.co.newStateOnFlush() refill_count := UFix(0) - acq_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush()) + acquire_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush()) + release_type := conf.co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc req := io.req_bits + sent_wb_req := Bool(false) state := Mux(conf.co.needsWriteback(io.req_bits.old_meta.state), s_wb_req, s_refill_req) when (io.req_bits.tag_match) { @@ -265,6 +297,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { } io.idx_match := (state != s_invalid) && idx_match + io.probe_idx_match := (state != s_invalid) && probe_idx_match io.mem_resp := req io.mem_resp.addr := Cat(req_idx, refill_count) << conf.ramoffbits io.tag := req.addr >> conf.untagbits @@ -281,12 +314,13 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { io.wb_req.bits.idx := req_idx io.wb_req.bits.way_en := req.way_en io.wb_req.bits.client_xact_id := Bits(id) + io.wb_req.bits.r_type := conf.co.getReleaseTypeOnVoluntaryWriteback() io.probe_writeback.ready := (state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match io.probe_refill.ready := (state != s_refill_resp && state != s_drain_rpq) || !idx_match io.mem_req.valid := state === s_refill_req - io.mem_req.bits.a_type := acq_type + io.mem_req.bits.a_type := acquire_type io.mem_req.bits.addr := Cat(io.tag, req_idx).toUFix io.mem_req.bits.client_xact_id := Bits(id) io.mem_finish <> finish_q.io.deq @@ -319,7 +353,8 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { val mem_rep = (new PipeIO) { new Grant }.flip val mem_finish = (new FIFOIO) { new GrantAck } val wb_req = (new FIFOIO) { new WritebackReq } - val probe = (new FIFOIO) { Bool() }.flip + val mem_probe = (new FIFOIO) { new Probe }.flip + val self_probe = (new FIFOIO) { new InternalProbe } val fence_rdy = Bool(OUTPUT) } @@ -340,6 +375,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { val mem_req_arb = (new Arbiter(conf.nmshr)) { new Acquire } val mem_finish_arb = (new Arbiter(conf.nmshr)) { new GrantAck } val wb_req_arb = (new Arbiter(conf.nmshr)) { new WritebackReq } + val self_probe_arb = (new Arbiter(conf.nmshr+1)) { new InternalProbe } val replay_arb = (new Arbiter(conf.nmshr)) { new Replay() } val alloc_arb = (new Arbiter(conf.nmshr)) { Bool() } @@ -347,11 +383,18 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { val wb_probe_match = Mux1H(idxMatch, wbTagList) === io.req.bits.addr >> conf.untagbits var idx_match = Bool(false) + var probe_idx_match = Bool(false) var pri_rdy = Bool(false) var fence = Bool(false) var sec_rdy = Bool(false) var writeback_probe_rdy = Bool(true) var refill_probe_rdy = Bool(true) + var mem_probe_rdy = Bool(false) + + self_probe_arb.io.in(0).valid := io.mem_probe.valid && !probe_idx_match + self_probe_arb.io.in(0).bits := io.mem_probe.bits + self_probe_arb.io.in(0).bits.client_xact_id := UFix(0) // DNC + mem_probe_rdy = mem_probe_rdy || self_probe_arb.io.in(0).ready for (i <- 0 to conf.nmshr-1) { val mshr = new MSHR(i) @@ -367,14 +410,16 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { mshr.io.req_bits := io.req.bits mshr.io.req_sdq_id := sdq_alloc_id + mshr.io.mem_probe <> io.mem_probe mshr.io.meta_read <> meta_read_arb.io.in(i) mshr.io.meta_write <> meta_write_arb.io.in(i) mshr.io.mem_req <> mem_req_arb.io.in(i) mshr.io.mem_finish <> mem_finish_arb.io.in(i) mshr.io.wb_req <> wb_req_arb.io.in(i) + mshr.io.self_probe <> self_probe_arb.io.in(i+1) mshr.io.replay <> replay_arb.io.in(i) - mshr.io.probe_refill.valid := io.probe.valid && tag_match - mshr.io.probe_writeback.valid := io.probe.valid + mshr.io.probe_refill.valid := io.mem_probe.valid && tag_match + mshr.io.probe_writeback.valid := io.mem_probe.valid mshr.io.probe_writeback.bits := wb_probe_match mshr.io.mem_abort <> io.mem_abort @@ -385,8 +430,10 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { sec_rdy = sec_rdy || mshr.io.req_sec_rdy fence = fence || !mshr.io.req_pri_rdy idx_match = idx_match || mshr.io.idx_match + probe_idx_match = probe_idx_match || mshr.io.probe_idx_match refill_probe_rdy = refill_probe_rdy && mshr.io.probe_refill.ready writeback_probe_rdy = writeback_probe_rdy && mshr.io.probe_writeback.ready + mem_probe_rdy = mem_probe_rdy || mshr.io.mem_probe_ready } alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match @@ -396,12 +443,14 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { mem_req_arb.io.out <> io.mem_req mem_finish_arb.io.out <> io.mem_finish wb_req_arb.io.out <> io.wb_req + self_probe_arb.io.out <> io.self_probe io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy io.secondary_miss := idx_match io.mem_resp := memRespMux(io.mem_rep.bits.client_xact_id) io.fence_rdy := !fence - io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match) + io.mem_probe.ready := mem_probe_rdy + //io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match) val free_sdq = io.replay.fire() && isWrite(io.replay.bits.cmd) io.replay.bits.data := sdq(RegEn(replay_arb.io.out.bits.sdq_id, free_sdq)) @@ -421,13 +470,11 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component { val meta_read = (new FIFOIO) { new MetaReadReq } val data_req = (new FIFOIO) { new DataReadReq() } val data_resp = Bits(INPUT, conf.bitsperrow) - val mem_req = (new FIFOIO) { new Acquire } - val mem_req_data = (new FIFOIO) { new AcquireData } + val release = (new FIFOIO) { new Release } val release_data = (new FIFOIO) { new ReleaseData } } val valid = Reg(resetVal = Bool(false)) - val is_probe = Reg{Bool()} val r1_data_req_fired = Reg(resetVal = Bool(false)) val r2_data_req_fired = Reg(resetVal = Bool(false)) val cmd_sent = Reg{Bool()} @@ -442,7 +489,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component { cnt := cnt + 1 } - when (r2_data_req_fired && !Mux(is_probe, io.release_data.ready, io.mem_req_data.ready)) { + when (r2_data_req_fired && !io.release_data.ready) { r1_data_req_fired := false r2_data_req_fired := false cnt := cnt - Mux[UFix](r1_data_req_fired, 2, 1) @@ -452,20 +499,18 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component { valid := false } - when (valid && io.mem_req.ready) { + when (valid && io.release.ready) { cmd_sent := true } } when (io.probe.fire()) { valid := true - is_probe := true cmd_sent := true cnt := 0 req := io.probe.bits } when (io.req.fire()) { valid := true - is_probe := false cmd_sent := false cnt := 0 req := io.req.bits @@ -478,22 +523,21 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component { io.data_req.bits.way_en := req.way_en io.data_req.bits.addr := Cat(req.idx, cnt(log2Up(REFILL_CYCLES)-1,0)) << conf.ramoffbits - io.mem_req.valid := valid && !cmd_sent - io.mem_req.bits.a_type := conf.co.getAcquireTypeOnWriteback() - io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix - io.mem_req.bits.client_xact_id := req.client_xact_id - io.mem_req_data.valid := r2_data_req_fired && !is_probe - io.mem_req_data.bits.data := io.data_resp - io.release_data.valid := r2_data_req_fired && is_probe + io.release.valid := valid && !cmd_sent + io.release.bits.r_type := req.r_type + io.release.bits.addr := Cat(req.tag, req.idx).toUFix + io.release.bits.client_xact_id := req.client_xact_id + io.release.bits.master_xact_id := UFix(0) + io.release_data.valid := r2_data_req_fired io.release_data.bits.data := io.data_resp io.meta_read.valid := fire - io.meta_read.bits.addr := io.mem_req.bits.addr << conf.offbits + io.meta_read.bits.addr := io.release.bits.addr << conf.offbits } class ProbeUnit(implicit conf: DCacheConfig) extends Component { val io = new Bundle { - val req = (new FIFOIO) { new Probe }.flip + val req = (new FIFOIO) { new InternalProbe }.flip val rep = (new FIFOIO) { new Release } val meta_read = (new FIFOIO) { new MetaReadReq } val meta_write = (new FIFOIO) { new MetaWriteReq } @@ -507,7 +551,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component { val state = Reg(resetVal = s_invalid) val line_state = Reg() { UFix() } val way_en = Reg() { Bits() } - val req = Reg() { new Probe() } + val req = Reg() { new InternalProbe } val hit = way_en.orR when (state === s_meta_write && io.meta_write.ready) { @@ -529,7 +573,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component { state := s_release line_state := io.line_state way_en := io.way_en - when (!io.mshr_req.ready) { state := s_meta_read } + //when (!io.mshr_req.ready) { state := s_meta_read } } when (state === s_meta_resp) { state := s_mshr_req @@ -544,7 +588,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component { io.req.ready := state === s_invalid && !reset io.rep.valid := state === s_release - io.rep.bits := conf.co.newRelease(req, Mux(hit, line_state, conf.co.newStateOnFlush)) + io.rep.bits := conf.co.newRelease(req, Mux(hit, line_state, conf.co.newStateOnFlush), req.client_xact_id) io.meta_read.valid := state === s_meta_read io.meta_read.bits.addr := req.addr << UFix(conf.offbits) @@ -555,11 +599,13 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component { io.meta_write.bits.data.state := conf.co.newStateOnProbe(req, line_state) io.meta_write.bits.data.tag := req.addr >> UFix(conf.idxbits) - io.mshr_req.valid := state === s_mshr_req + //io.mshr_req.valid := state === s_mshr_req io.wb_req.valid := state === s_writeback_req io.wb_req.bits.way_en := way_en io.wb_req.bits.idx := req.addr io.wb_req.bits.tag := req.addr >> UFix(conf.idxbits) + io.wb_req.bits.r_type := UFix(0) // DNC + io.wb_req.bits.client_xact_id := UFix(0) // DNC } class MetaDataArray(implicit conf: DCacheConfig) extends Component { @@ -919,8 +965,18 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio mshr.io.mem_abort.valid := io.mem.abort.valid mshr.io.mem_abort.bits := io.mem.abort.bits.payload io.mem.abort.ready := Bool(true) + mshr.io.mem_probe <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe) when (mshr.io.req.fire()) { replacer.miss } + io.mem.acquire.valid := mshr.io.mem_req.valid && prober.io.req.ready + mshr.io.mem_req.ready := io.mem.acquire.ready && prober.io.req.ready + io.mem.acquire.bits.payload := mshr.io.mem_req.bits + //TODO io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_req) ??? + //TODO io.mem.acquire_data should be connected to uncached store data generator + //io.mem.acquire_data <> FIFOedLogicalNetworkIOWrapper(TODO) + io.mem.acquire_data.valid := Bool(false) + io.mem.acquire_data.bits.payload.data := UFix(0) + // replays readArb.io.in(1).valid := mshr.io.replay.valid readArb.io.in(1).bits := mshr.io.replay.bits @@ -931,9 +987,12 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio metaWriteArb.io.in(0) <> mshr.io.meta_write // probes - prober.io.req <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe) - FIFOedLogicalNetworkIOWrapper(prober.io.rep) <> io.mem.release - prober.io.mshr_req <> mshr.io.probe + val releaseArb = (new Arbiter(2)) { new Release } + FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release + + prober.io.req <> mshr.io.self_probe + prober.io.rep <> releaseArb.io.in(1) + //prober.io.mshr_req <> mshr.io.probe prober.io.wb_req <> wb.io.probe prober.io.way_en := s2_tag_match_way prober.io.line_state := s2_hit_state @@ -953,6 +1012,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio wb.io.meta_read <> metaReadArb.io.in(3) wb.io.data_req <> readArb.io.in(2) wb.io.data_resp := s2_data_corrected + releaseArb.io.in(0) <> wb.io.release FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release_data // store->load bypassing @@ -1016,13 +1076,5 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio io.cpu.resp.bits.data_subword := loadgen.byte io.cpu.resp.bits.store_data := s2_req.data - val acquire_arb = (new Arbiter(2)) { new Acquire } - acquire_arb.io.in(0) <> wb.io.mem_req - acquire_arb.io.in(1).valid := mshr.io.mem_req.valid && prober.io.req.ready - mshr.io.mem_req.ready := acquire_arb.io.in(1).ready && prober.io.req.ready - acquire_arb.io.in(1).bits := mshr.io.mem_req.bits - io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(acquire_arb.io.out) - - io.mem.acquire_data <> FIFOedLogicalNetworkIOWrapper(wb.io.mem_req_data) io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_finish) } diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index b4ddbd05..9ac249b1 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -24,6 +24,7 @@ case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: Coherenc class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent { val memPorts = 2 + confIn.vec + val dcachePortID = 0 implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen) implicit val lnConf = confIn.lnConf implicit val conf = confIn.copy(dcache = dcConf) @@ -38,7 +39,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon val dcache = new HellaCache val arbiter = new MemArbiter(memPorts) - arbiter.io.requestor(0) <> dcache.io.mem + arbiter.io.requestor(dcachePortID) <> dcache.io.mem arbiter.io.requestor(1) <> icache.io.mem io.tilelink.acquire <> arbiter.io.mem.acquire @@ -47,8 +48,11 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon arbiter.io.mem.grant <> io.tilelink.grant io.tilelink.grant_ack <> arbiter.io.mem.grant_ack dcache.io.mem.probe <> io.tilelink.probe - io.tilelink.release <> dcache.io.mem.release io.tilelink.release_data <> dcache.io.mem.release_data + io.tilelink.release.valid := dcache.io.mem.release.valid + dcache.io.mem.release.ready := io.tilelink.release.ready + io.tilelink.release.bits := dcache.io.mem.release.bits + io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortID, log2Up(memPorts))) // Mimic client id extension done by MemArbiter for Acquires from either cache) if (conf.vec) { val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB) From ea9d0b771efd1acf32e149b636fdb2af03669add Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 19 Mar 2013 15:29:40 -0700 Subject: [PATCH 3/5] remove aborts; simplify probes --- rocket/src/main/scala/arbiter.scala | 11 ---- rocket/src/main/scala/htif.scala | 11 ---- rocket/src/main/scala/icache.scala | 1 - rocket/src/main/scala/nbdcache.scala | 81 +++++----------------------- rocket/src/main/scala/tile.scala | 1 - 5 files changed, 14 insertions(+), 91 deletions(-) diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index 4b8529e6..871a8595 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -50,7 +50,6 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Comp class UncachedRequestorIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }} - val abort = (new MasterSourcedIO) {(new LogicalNetworkIO){new Abort }} val grant = (new MasterSourcedIO) {(new LogicalNetworkIO){new Grant }} val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }} } @@ -101,14 +100,4 @@ class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Com io.requestor(i).grant.bits := io.mem.grant.bits io.requestor(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n)) } - - for (i <- 0 until n) - { - val tag = io.mem.abort.bits.payload.client_xact_id - io.requestor(i).abort.valid := io.mem.abort.valid && tag(log2Up(n)-1,0) === UFix(i) - io.requestor(i).abort.bits := io.mem.abort.bits - io.requestor(i).abort.bits.payload.client_xact_id := tag >> UFix(log2Up(n)) - } - - io.mem.abort.ready := Bool(true) } diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 85c6bb50..6e81f99a 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -105,15 +105,12 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo val mem_acked = Reg(resetVal = Bool(false)) val mem_gxid = Reg() { Bits() } val mem_needs_ack = Reg() { Bool() } - val mem_nacked = Reg(resetVal = Bool(false)) when (io.mem.grant.valid) { mem_acked := Bool(true) mem_gxid := io.mem.grant.bits.payload.master_xact_id mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload) } io.mem.grant.ready := Bool(true) - when (io.mem.abort.valid) { mem_nacked := Bool(true) } - io.mem.abort.ready := Bool(true) val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(9) { UFix() } val state = Reg(resetVal = state_rx) @@ -137,20 +134,12 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo mem_cnt := mem_cnt + UFix(1) } when (state === state_mem_wresp) { - when (mem_nacked) { - state := state_mem_req - mem_nacked := Bool(false) - } when (mem_acked) { state := state_mem_finish mem_acked := Bool(false) } } when (state === state_mem_rdata) { - when (mem_nacked) { - state := state_mem_req - mem_nacked := Bool(false) - } when (io.mem.grant.valid) { when (mem_cnt.andR) { state := state_mem_finish diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 764ba9ee..8ddd9823 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -259,7 +259,6 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte when (io.mem.acquire.ready && finish_q.io.enq.ready) { state := s_refill_wait } } is (s_refill_wait) { - when (io.mem.abort.valid) { state := s_request } when (io.mem.grant.valid) { state := s_refill } } is (s_refill) { diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 88adc3be..acdabd5a 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -178,11 +178,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val meta_read = (new FIFOIO) { new MetaReadReq } val meta_write = (new FIFOIO) { new MetaWriteReq } val replay = (new FIFOIO) { new Replay() } - val mem_abort = (new PipeIO) { new Abort }.flip val mem_rep = (new PipeIO) { new Grant }.flip - val mem_probe = (new PipeIO) { new Probe }.flip - val mem_probe_ready = Bool(OUTPUT) - val self_probe = (new FIFOIO) { new InternalProbe } val mem_finish = (new FIFOIO) { new GrantAck } val wb_req = (new FIFOIO) { new WritebackReq } val probe_writeback = (new FIFOIO) { Bool() }.flip @@ -197,32 +193,16 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val line_state = Reg { UFix() } val refill_count = Reg { UFix(width = log2Up(REFILL_CYCLES)) } val req = Reg { new MSHRReq() } - val sent_wb_req = Reg { Bool() } val req_cmd = io.req_bits.cmd val req_idx = req.addr(conf.untagbits-1,conf.offbits) val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits) - val probe_idx_match = req_idx === io.mem_probe.bits.addr(conf.untagbits-1,conf.offbits) val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits)) - val abort = io.mem_abort.valid && io.mem_abort.bits.client_xact_id === UFix(id) val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id) val refill_done = reply && refill_count.andR val wb_done = reply && (state === s_wb_resp) - val probe_wb_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.old_meta.tag - val probe_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.addr >> conf.untagbits - val handle_probe = (state != s_invalid) && probe_idx_match - val kill_probe = sent_wb_req && probe_wb_tag_match && conf.co.pendingVoluntaryReleaseIsSufficient(release_type, io.mem_probe.bits.p_type) - val probe_q = (new Queue(1, pipe = true, flow = true)) { new Probe } - probe_q.io.enq.valid := io.mem_probe.valid && handle_probe && sent_wb_req && !kill_probe - io.mem_probe_ready := probe_q.io.enq.ready && handle_probe - probe_q.io.enq.bits := io.mem_probe.bits - io.self_probe.valid := probe_q.io.deq.valid && (state != s_wb_resp) - probe_q.io.deq.ready := io.self_probe.ready && (state != s_wb_resp) - io.self_probe.bits := probe_q.io.deq.bits - io.self_probe.bits.client_xact_id := UFix(id) - val rpq = (new Queue(conf.nrpq)) { new Replay } rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(req_cmd) rpq.io.enq.bits := io.req_bits @@ -232,7 +212,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck } finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_rep.bits) finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id - io.wb_req.valid := Bool(false) when (state === s_drain_rpq && !rpq.io.deq.valid && !finish_q.io.deq.valid) { state := s_invalid @@ -250,28 +229,18 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { refill_count := refill_count + UFix(1) line_state := conf.co.newStateOnGrant(io.mem_rep.bits, io.mem_req.bits) } - when (abort) { state := s_refill_req } } when (state === s_refill_req) { - when (abort) { state := s_refill_req } - .elsewhen (io.mem_req.ready) { state := s_refill_resp } + when (io.mem_req.ready) { state := s_refill_resp } } when (state === s_meta_clear && io.meta_write.ready) { state := s_refill_req } when (state === s_wb_resp) { when (reply) { state := s_meta_clear } - when (abort) { state := s_wb_req } } - when (state === s_wb_req) { - io.wb_req.valid := Bool(true) - when (io.probe_writeback.valid && idx_match) { - io.wb_req.valid := Bool(false) - when (io.probe_writeback.bits) { state := s_refill_req } - }.elsewhen (io.wb_req.ready) { - sent_wb_req := Bool(true) - state := s_wb_resp - } + when (state === s_wb_req && io.wb_req.ready) { + state := s_wb_resp } when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req @@ -283,7 +252,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { acquire_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush()) release_type := conf.co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc req := io.req_bits - sent_wb_req := Bool(false) state := Mux(conf.co.needsWriteback(io.req_bits.old_meta.state), s_wb_req, s_refill_req) when (io.req_bits.tag_match) { @@ -297,7 +265,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { } io.idx_match := (state != s_invalid) && idx_match - io.probe_idx_match := (state != s_invalid) && probe_idx_match io.mem_resp := req io.mem_resp.addr := Cat(req_idx, refill_count) << conf.ramoffbits io.tag := req.addr >> conf.untagbits @@ -310,14 +277,15 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { io.meta_write.bits.data.tag := io.tag io.meta_write.bits.way_en := req.way_en + io.wb_req.valid := state === s_wb_req io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.way_en := req.way_en io.wb_req.bits.client_xact_id := Bits(id) io.wb_req.bits.r_type := conf.co.getReleaseTypeOnVoluntaryWriteback() - io.probe_writeback.ready := (state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match - io.probe_refill.ready := (state != s_refill_resp && state != s_drain_rpq) || !idx_match + io.probe_writeback.ready := (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match + io.probe_refill.ready := (state != s_refill_resp && state != s_meta_write_req && state != s_meta_write_resp && state != s_drain_rpq) || !idx_match io.mem_req.valid := state === s_refill_req io.mem_req.bits.a_type := acquire_type @@ -349,12 +317,10 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { val meta_read = (new FIFOIO) { new MetaReadReq } val meta_write = (new FIFOIO) { new MetaWriteReq } val replay = (new FIFOIO) { new Replay } - val mem_abort = (new PipeIO) { new Abort }.flip val mem_rep = (new PipeIO) { new Grant }.flip val mem_finish = (new FIFOIO) { new GrantAck } val wb_req = (new FIFOIO) { new WritebackReq } - val mem_probe = (new FIFOIO) { new Probe }.flip - val self_probe = (new FIFOIO) { new InternalProbe } + val probe = (new FIFOIO) { new Bool() }.flip val fence_rdy = Bool(OUTPUT) } @@ -375,7 +341,6 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { val mem_req_arb = (new Arbiter(conf.nmshr)) { new Acquire } val mem_finish_arb = (new Arbiter(conf.nmshr)) { new GrantAck } val wb_req_arb = (new Arbiter(conf.nmshr)) { new WritebackReq } - val self_probe_arb = (new Arbiter(conf.nmshr+1)) { new InternalProbe } val replay_arb = (new Arbiter(conf.nmshr)) { new Replay() } val alloc_arb = (new Arbiter(conf.nmshr)) { Bool() } @@ -383,18 +348,11 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { val wb_probe_match = Mux1H(idxMatch, wbTagList) === io.req.bits.addr >> conf.untagbits var idx_match = Bool(false) - var probe_idx_match = Bool(false) var pri_rdy = Bool(false) var fence = Bool(false) var sec_rdy = Bool(false) var writeback_probe_rdy = Bool(true) var refill_probe_rdy = Bool(true) - var mem_probe_rdy = Bool(false) - - self_probe_arb.io.in(0).valid := io.mem_probe.valid && !probe_idx_match - self_probe_arb.io.in(0).bits := io.mem_probe.bits - self_probe_arb.io.in(0).bits.client_xact_id := UFix(0) // DNC - mem_probe_rdy = mem_probe_rdy || self_probe_arb.io.in(0).ready for (i <- 0 to conf.nmshr-1) { val mshr = new MSHR(i) @@ -410,19 +368,16 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { mshr.io.req_bits := io.req.bits mshr.io.req_sdq_id := sdq_alloc_id - mshr.io.mem_probe <> io.mem_probe mshr.io.meta_read <> meta_read_arb.io.in(i) mshr.io.meta_write <> meta_write_arb.io.in(i) mshr.io.mem_req <> mem_req_arb.io.in(i) mshr.io.mem_finish <> mem_finish_arb.io.in(i) mshr.io.wb_req <> wb_req_arb.io.in(i) - mshr.io.self_probe <> self_probe_arb.io.in(i+1) mshr.io.replay <> replay_arb.io.in(i) - mshr.io.probe_refill.valid := io.mem_probe.valid && tag_match - mshr.io.probe_writeback.valid := io.mem_probe.valid + mshr.io.probe_refill.valid := io.probe.valid && tag_match + mshr.io.probe_writeback.valid := io.probe.valid mshr.io.probe_writeback.bits := wb_probe_match - mshr.io.mem_abort <> io.mem_abort mshr.io.mem_rep <> io.mem_rep memRespMux(i) := mshr.io.mem_resp @@ -430,10 +385,8 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { sec_rdy = sec_rdy || mshr.io.req_sec_rdy fence = fence || !mshr.io.req_pri_rdy idx_match = idx_match || mshr.io.idx_match - probe_idx_match = probe_idx_match || mshr.io.probe_idx_match refill_probe_rdy = refill_probe_rdy && mshr.io.probe_refill.ready writeback_probe_rdy = writeback_probe_rdy && mshr.io.probe_writeback.ready - mem_probe_rdy = mem_probe_rdy || mshr.io.mem_probe_ready } alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match @@ -443,14 +396,12 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { mem_req_arb.io.out <> io.mem_req mem_finish_arb.io.out <> io.mem_finish wb_req_arb.io.out <> io.wb_req - self_probe_arb.io.out <> io.self_probe io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy io.secondary_miss := idx_match io.mem_resp := memRespMux(io.mem_rep.bits.client_xact_id) io.fence_rdy := !fence - io.mem_probe.ready := mem_probe_rdy - //io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match) + io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match) val free_sdq = io.replay.fire() && isWrite(io.replay.bits.cmd) io.replay.bits.data := sdq(RegEn(replay_arb.io.out.bits.sdq_id, free_sdq)) @@ -573,7 +524,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component { state := s_release line_state := io.line_state way_en := io.way_en - //when (!io.mshr_req.ready) { state := s_meta_read } + when (!io.mshr_req.ready) { state := s_meta_read } } when (state === s_meta_resp) { state := s_mshr_req @@ -599,7 +550,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component { io.meta_write.bits.data.state := conf.co.newStateOnProbe(req, line_state) io.meta_write.bits.data.tag := req.addr >> UFix(conf.idxbits) - //io.mshr_req.valid := state === s_mshr_req + io.mshr_req.valid := state === s_mshr_req io.wb_req.valid := state === s_writeback_req io.wb_req.bits.way_en := way_en io.wb_req.bits.idx := req.addr @@ -962,10 +913,6 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio mshr.io.mem_rep.valid := io.mem.grant.fire() mshr.io.mem_rep.bits := io.mem.grant.bits.payload - mshr.io.mem_abort.valid := io.mem.abort.valid - mshr.io.mem_abort.bits := io.mem.abort.bits.payload - io.mem.abort.ready := Bool(true) - mshr.io.mem_probe <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe) when (mshr.io.req.fire()) { replacer.miss } io.mem.acquire.valid := mshr.io.mem_req.valid && prober.io.req.ready @@ -990,9 +937,9 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio val releaseArb = (new Arbiter(2)) { new Release } FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release - prober.io.req <> mshr.io.self_probe + prober.io.req <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe) prober.io.rep <> releaseArb.io.in(1) - //prober.io.mshr_req <> mshr.io.probe + prober.io.mshr_req <> mshr.io.probe prober.io.wb_req <> wb.io.probe prober.io.way_en := s2_tag_match_way prober.io.line_state := s2_hit_state diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 9ac249b1..2cbfd24c 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -44,7 +44,6 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon io.tilelink.acquire <> arbiter.io.mem.acquire io.tilelink.acquire_data <> dcache.io.mem.acquire_data - arbiter.io.mem.abort <> io.tilelink.abort arbiter.io.mem.grant <> io.tilelink.grant io.tilelink.grant_ack <> arbiter.io.mem.grant_ack dcache.io.mem.probe <> io.tilelink.probe From 6d2541acedaeeb94fcce39dda671584e364b2c02 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 28 Feb 2013 21:03:37 -0800 Subject: [PATCH 4/5] nTiles -> nClients in LogicalNetworkConfig --- rocket/src/main/scala/core.scala | 2 +- rocket/src/main/scala/dpath.scala | 2 +- rocket/src/main/scala/dpath_util.scala | 2 +- rocket/src/main/scala/htif.scala | 20 ++++++++++---------- rocket/src/main/scala/tile.scala | 2 +- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala index 2c27e514..09fad98c 100644 --- a/rocket/src/main/scala/core.scala +++ b/rocket/src/main/scala/core.scala @@ -8,7 +8,7 @@ import Util._ class RocketIO(implicit conf: RocketConfiguration) extends Bundle { - val host = new HTIFIO(conf.lnConf.nTiles) + val host = new HTIFIO(conf.lnConf.nClients) val imem = new CPUFrontendIO()(conf.icache) val vimem = new CPUFrontendIO()(conf.icache) val dmem = new HellaCacheIO()(conf.dcache) diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index e7387a27..ffe039c1 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -10,7 +10,7 @@ import hwacha._ class Datapath(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { - val host = new HTIFIO(conf.lnConf.nTiles) + val host = new HTIFIO(conf.lnConf.nClients) val ctrl = (new CtrlDpathIO).flip val dmem = new HellaCacheIO()(conf.dcache) val ptw = (new DatapathPTWIO).flip diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 131ae28c..bce859c9 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -104,7 +104,7 @@ object PCR class PCR(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { - val host = new HTIFIO(conf.lnConf.nTiles) + val host = new HTIFIO(conf.lnConf.nClients) val r = new ioReadPort(conf.nxpr, conf.xprlen) val w = new ioWritePort(conf.nxpr, conf.xprlen) diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 6e81f99a..365380ae 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -41,7 +41,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo implicit val lnConf = conf.ln val io = new Bundle { val host = new HostIO(w) - val cpu = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles).flip } + val cpu = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients).flip } val mem = new TileLinkIO()(conf.ln) } @@ -82,7 +82,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() } val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0) - val pcr_coreid = if (conf.ln.nTiles == 1) UFix(0) else addr(20+log2Up(conf.ln.nTiles),20) + val pcr_coreid = if (conf.ln.nClients == 1) UFix(0) else addr(20+log2Up(conf.ln.nClients),20) val pcr_wdata = packet_ram(0) val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR @@ -182,19 +182,19 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo io.mem.release.valid := Bool(false) io.mem.release_data.valid := Bool(false) - io.mem.acquire.bits.header.src := UFix(conf.ln.nTiles) + io.mem.acquire.bits.header.src := UFix(conf.ln.nClients) io.mem.acquire.bits.header.dst := UFix(0) - io.mem.acquire_data.bits.header.src := UFix(conf.ln.nTiles) + io.mem.acquire_data.bits.header.src := UFix(conf.ln.nClients) io.mem.acquire_data.bits.header.dst := UFix(0) - io.mem.release.bits.header.src := UFix(conf.ln.nTiles) + io.mem.release.bits.header.src := UFix(conf.ln.nClients) io.mem.release.bits.header.dst := UFix(0) - io.mem.release_data.bits.header.src := UFix(conf.ln.nTiles) + io.mem.release_data.bits.header.src := UFix(conf.ln.nClients) io.mem.release_data.bits.header.dst := UFix(0) - io.mem.grant_ack.bits.header.src := UFix(conf.ln.nTiles) + io.mem.grant_ack.bits.header.src := UFix(conf.ln.nClients) io.mem.grant_ack.bits.header.dst := UFix(0) - val pcrReadData = Vec(conf.ln.nTiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } } - for (i <- 0 until conf.ln.nTiles) { + val pcrReadData = Vec(conf.ln.nClients) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } } + for (i <- 0 until conf.ln.nClients) { val my_reset = Reg(resetVal = Bool(true)) val my_ipi = Reg(resetVal = Bool(false)) @@ -211,7 +211,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo } cpu.ipi_rep.valid := my_ipi cpu.ipi_req.ready := Bool(true) - for (j <- 0 until conf.ln.nTiles) { + for (j <- 0 until conf.ln.nClients) { when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) { my_ipi := Bool(true) } diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 2cbfd24c..be141b77 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -31,7 +31,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon val io = new Bundle { val tilelink = new TileLinkIO - val host = new HTIFIO(lnConf.nTiles) + val host = new HTIFIO(lnConf.nClients) } val core = new Core From 273bd34091288cd01fe7ad42ee2dc026a76f0696 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 20 Mar 2013 14:05:12 -0700 Subject: [PATCH 5/5] Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants. --- rocket/src/main/scala/arbiter.scala | 54 ---------------------------- rocket/src/main/scala/htif.scala | 18 +++------- rocket/src/main/scala/icache.scala | 5 +-- rocket/src/main/scala/nbdcache.scala | 39 ++++++++++---------- rocket/src/main/scala/tile.scala | 22 ++++++------ 5 files changed, 40 insertions(+), 98 deletions(-) diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index 871a8595..ac842d85 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -47,57 +47,3 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Comp resp.bits.replay := io.mem.resp.bits.replay && tag_hit } } - -class UncachedRequestorIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { - val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }} - val grant = (new MasterSourcedIO) {(new LogicalNetworkIO){new Grant }} - val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }} -} - -class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Component { - val io = new Bundle { - val mem = new UncachedRequestorIO - val requestor = Vec(n) { new UncachedRequestorIO }.flip - } - - var acq_bits = new Acquire - acq_bits := io.requestor(n-1).acquire.bits.payload - acq_bits.client_xact_id := Cat(io.requestor(n-1).acquire.bits.payload.client_xact_id, UFix(n-1, log2Up(n))) - for (i <- n-2 to 0 by -1) - { - var my_acq_bits = new Acquire - my_acq_bits := io.requestor(i).acquire.bits.payload - my_acq_bits.client_xact_id := Cat(io.requestor(i).acquire.bits.payload.client_xact_id, UFix(i, log2Up(n))) - - acq_bits = Mux(io.requestor(i).acquire.valid, my_acq_bits, acq_bits) - } - - io.mem.acquire.bits.payload := acq_bits - io.mem.acquire.valid := io.requestor.map(_.acquire.valid).reduce(_||_) - io.requestor(0).acquire.ready := io.mem.acquire.ready - for (i <- 1 until n) - io.requestor(i).acquire.ready := io.requestor(i-1).acquire.ready && !io.requestor(i-1).acquire.valid - - var ga_bits = io.requestor(n-1).grant_ack.bits - for (i <- n-2 to 0 by -1) - ga_bits = Mux(io.requestor(i).grant_ack.valid, io.requestor(i).grant_ack.bits, ga_bits) - - io.mem.grant_ack.bits := ga_bits - io.mem.grant_ack.valid := io.requestor.map(_.grant_ack.valid).reduce(_||_) - io.requestor(0).grant_ack.ready := io.mem.grant_ack.ready - for (i <- 1 until n) - io.requestor(i).grant_ack.ready := io.requestor(i-1).grant_ack.ready && !io.requestor(i-1).grant_ack.valid - - io.mem.grant.ready := Bool(false) - for (i <- 0 until n) - { - val tag = io.mem.grant.bits.payload.client_xact_id - io.requestor(i).grant.valid := Bool(false) - when (tag(log2Up(n)-1,0) === UFix(i)) { - io.requestor(i).grant.valid := io.mem.grant.valid - io.mem.grant.ready := io.requestor(i).grant.ready - } - io.requestor(i).grant.bits := io.mem.grant.bits - io.requestor(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n)) - } -} diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 365380ae..d7aef576 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -36,7 +36,7 @@ class HTIFIO(ntiles: Int) extends Bundle val ipi_rep = (new FIFOIO) { Bool() }.flip } -class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Component with ClientCoherenceAgent +class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component with ClientCoherenceAgent { implicit val lnConf = conf.ln val io = new Bundle { @@ -104,10 +104,12 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo val mem_acked = Reg(resetVal = Bool(false)) val mem_gxid = Reg() { Bits() } + val mem_gsrc = Reg() { UFix(width = conf.ln.idBits) } val mem_needs_ack = Reg() { Bool() } when (io.mem.grant.valid) { mem_acked := Bool(true) mem_gxid := io.mem.grant.bits.payload.master_xact_id + mem_gsrc := io.mem.grant.bits.header.src mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload) } io.mem.grant.ready := Bool(true) @@ -173,26 +175,16 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3) val co = conf.co.asInstanceOf[CoherencePolicyWithUncached] x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteAcquire(init_addr, UFix(0)), co.getUncachedReadAcquire(init_addr, UFix(0))) - io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq) + io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq, UFix(conf.ln.nClients), UFix(0)) io.mem.acquire_data.valid:= state === state_mem_wdata io.mem.acquire_data.bits.payload.data := mem_req_data io.mem.grant_ack.valid := (state === state_mem_finish) && mem_needs_ack io.mem.grant_ack.bits.payload.master_xact_id := mem_gxid + io.mem.grant_ack.bits.header.dst := mem_gsrc io.mem.probe.ready := Bool(false) io.mem.release.valid := Bool(false) io.mem.release_data.valid := Bool(false) - io.mem.acquire.bits.header.src := UFix(conf.ln.nClients) - io.mem.acquire.bits.header.dst := UFix(0) - io.mem.acquire_data.bits.header.src := UFix(conf.ln.nClients) - io.mem.acquire_data.bits.header.dst := UFix(0) - io.mem.release.bits.header.src := UFix(conf.ln.nClients) - io.mem.release.bits.header.dst := UFix(0) - io.mem.release_data.bits.header.src := UFix(conf.ln.nClients) - io.mem.release_data.bits.header.dst := UFix(0) - io.mem.grant_ack.bits.header.src := UFix(conf.ln.nClients) - io.mem.grant_ack.bits.header.dst := UFix(0) - val pcrReadData = Vec(conf.ln.nClients) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } } for (i <- 0 until conf.ln.nClients) { val my_reset = Reg(resetVal = Bool(true)) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 8ddd9823..f72361af 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -54,7 +54,7 @@ class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) ex { val io = new Bundle { val cpu = new CPUFrontendIO()(c).flip - val mem = new UncachedRequestorIO + val mem = new UncachedTileLinkIO } val btb = new rocketDpathBTB(c.nbtb) @@ -134,7 +134,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte val datablock = Bits(width = c.databits) }) val invalidate = Bool(INPUT) - val mem = new UncachedRequestorIO + val mem = new UncachedTileLinkIO } val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(4) { UFix() } @@ -246,6 +246,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte io.resp.valid := s2_hit io.mem.acquire.valid := (state === s_request) && finish_q.io.enq.ready io.mem.acquire.bits.payload := c.co.getUncachedReadAcquire(s2_addr >> UFix(c.offbits), UFix(0)) + io.mem.acquire_data.valid := Bool(false) io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(finish_q.io.deq) io.mem.grant.ready := Bool(true) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index acdabd5a..0d6b562d 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -124,7 +124,7 @@ class DataWriteReq(implicit conf: DCacheConfig) extends Bundle { } class InternalProbe(implicit conf: DCacheConfig) extends Probe { - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) + val client_xact_id = Bits(width = CLIENT_XACT_ID_MAX_BITS) override def clone = new InternalProbe().asInstanceOf[this.type] } @@ -133,7 +133,7 @@ class WritebackReq(implicit conf: DCacheConfig) extends Bundle { val tag = Bits(width = conf.tagbits) val idx = Bits(width = conf.idxbits) val way_en = Bits(width = conf.ways) - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) + val client_xact_id = Bits(width = CLIENT_XACT_ID_MAX_BITS) val r_type = UFix(width = RELEASE_TYPE_MAX_BITS) override def clone = new WritebackReq().asInstanceOf[this.type] @@ -160,7 +160,7 @@ class MetaWriteReq(implicit conf: DCacheConfig) extends Bundle { override def clone = new MetaWriteReq().asInstanceOf[this.type] } -class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { +class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component { val io = new Bundle { val req_pri_val = Bool(INPUT) val req_pri_rdy = Bool(OUTPUT) @@ -178,8 +178,8 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val meta_read = (new FIFOIO) { new MetaReadReq } val meta_write = (new FIFOIO) { new MetaWriteReq } val replay = (new FIFOIO) { new Replay() } - val mem_rep = (new PipeIO) { new Grant }.flip - val mem_finish = (new FIFOIO) { new GrantAck } + val mem_grant = (new PipeIO) { (new LogicalNetworkIO) {new Grant} }.flip + val mem_finish = (new FIFOIO) { (new LogicalNetworkIO) {new GrantAck} } val wb_req = (new FIFOIO) { new WritebackReq } val probe_writeback = (new FIFOIO) { Bool() }.flip val probe_refill = (new FIFOIO) { Bool() }.flip @@ -199,7 +199,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits) val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits)) - val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id) + val reply = io.mem_grant.valid && io.mem_grant.bits.payload.client_xact_id === UFix(id) val refill_done = reply && refill_count.andR val wb_done = reply && (state === s_wb_resp) @@ -209,9 +209,10 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { rpq.io.enq.bits.sdq_id := io.req_sdq_id rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid - val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck } - finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_rep.bits) - finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id + val finish_q = (new Queue(2 /* wb + refill */)) { (new LogicalNetworkIO){new GrantAck} } + finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_grant.bits.payload) + finish_q.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id + finish_q.io.enq.bits.header.dst := io.mem_grant.bits.header.src when (state === s_drain_rpq && !rpq.io.deq.valid && !finish_q.io.deq.valid) { state := s_invalid @@ -227,7 +228,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { when (refill_done) { state := s_meta_write_req } when (reply) { refill_count := refill_count + UFix(1) - line_state := conf.co.newStateOnGrant(io.mem_rep.bits, io.mem_req.bits) + line_state := conf.co.newStateOnGrant(io.mem_grant.bits.payload, io.mem_req.bits) } } when (state === s_refill_req) { @@ -307,7 +308,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { } } -class MSHRFile(implicit conf: DCacheConfig) extends Component { +class MSHRFile(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new MSHRReq }.flip val secondary_miss = Bool(OUTPUT) @@ -317,8 +318,8 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { val meta_read = (new FIFOIO) { new MetaReadReq } val meta_write = (new FIFOIO) { new MetaWriteReq } val replay = (new FIFOIO) { new Replay } - val mem_rep = (new PipeIO) { new Grant }.flip - val mem_finish = (new FIFOIO) { new GrantAck } + val mem_grant = (new PipeIO) { (new LogicalNetworkIO){new Grant} }.flip + val mem_finish = (new FIFOIO) { (new LogicalNetworkIO){new GrantAck} } val wb_req = (new FIFOIO) { new WritebackReq } val probe = (new FIFOIO) { new Bool() }.flip @@ -339,7 +340,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { val meta_read_arb = (new Arbiter(conf.nmshr)) { new MetaReadReq } val meta_write_arb = (new Arbiter(conf.nmshr)) { new MetaWriteReq } val mem_req_arb = (new Arbiter(conf.nmshr)) { new Acquire } - val mem_finish_arb = (new Arbiter(conf.nmshr)) { new GrantAck } + val mem_finish_arb = (new Arbiter(conf.nmshr)) { (new LogicalNetworkIO){new GrantAck} } val wb_req_arb = (new Arbiter(conf.nmshr)) { new WritebackReq } val replay_arb = (new Arbiter(conf.nmshr)) { new Replay() } val alloc_arb = (new Arbiter(conf.nmshr)) { Bool() } @@ -378,7 +379,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { mshr.io.probe_writeback.valid := io.probe.valid mshr.io.probe_writeback.bits := wb_probe_match - mshr.io.mem_rep <> io.mem_rep + mshr.io.mem_grant <> io.mem_grant memRespMux(i) := mshr.io.mem_resp pri_rdy = pri_rdy || mshr.io.req_pri_rdy @@ -399,7 +400,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component { io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy io.secondary_miss := idx_match - io.mem_resp := memRespMux(io.mem_rep.bits.client_xact_id) + io.mem_resp := memRespMux(io.mem_grant.bits.payload.client_xact_id) io.fence_rdy := !fence io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match) @@ -911,8 +912,8 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio mshr.io.req.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) mshr.io.req.bits.data := s2_req.data - mshr.io.mem_rep.valid := io.mem.grant.fire() - mshr.io.mem_rep.bits := io.mem.grant.bits.payload + mshr.io.mem_grant.valid := io.mem.grant.fire() + mshr.io.mem_grant.bits := io.mem.grant.bits when (mshr.io.req.fire()) { replacer.miss } io.mem.acquire.valid := mshr.io.mem_req.valid && prober.io.req.ready @@ -1023,5 +1024,5 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio io.cpu.resp.bits.data_subword := loadgen.byte io.cpu.resp.bits.store_data := s2_req.data - io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_finish) + io.mem.grant_ack <> mshr.io.mem_finish } diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index be141b77..1689a66d 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -24,7 +24,9 @@ case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: Coherenc class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent { val memPorts = 2 + confIn.vec - val dcachePortID = 0 + val dcachePortId = 0 + val icachePortId = 1 + val vicachePortId = 2 implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen) implicit val lnConf = confIn.lnConf implicit val conf = confIn.copy(dcache = dcConf) @@ -38,24 +40,24 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon val icache = new Frontend()(confIn.icache, lnConf) val dcache = new HellaCache - val arbiter = new MemArbiter(memPorts) - arbiter.io.requestor(dcachePortID) <> dcache.io.mem - arbiter.io.requestor(1) <> icache.io.mem + val arbiter = new UncachedTileLinkIOArbiter(memPorts) + arbiter.io.in(dcachePortId) <> dcache.io.mem + arbiter.io.in(icachePortId) <> icache.io.mem - io.tilelink.acquire <> arbiter.io.mem.acquire - io.tilelink.acquire_data <> dcache.io.mem.acquire_data - arbiter.io.mem.grant <> io.tilelink.grant - io.tilelink.grant_ack <> arbiter.io.mem.grant_ack + io.tilelink.acquire <> arbiter.io.out.acquire + io.tilelink.acquire_data <> arbiter.io.out.acquire_data + arbiter.io.out.grant <> io.tilelink.grant + io.tilelink.grant_ack <> arbiter.io.out.grant_ack dcache.io.mem.probe <> io.tilelink.probe io.tilelink.release_data <> dcache.io.mem.release_data io.tilelink.release.valid := dcache.io.mem.release.valid dcache.io.mem.release.ready := io.tilelink.release.ready io.tilelink.release.bits := dcache.io.mem.release.bits - io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortID, log2Up(memPorts))) // Mimic client id extension done by MemArbiter for Acquires from either cache) + io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client) if (conf.vec) { val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB) - arbiter.io.requestor(2) <> vicache.io.mem + arbiter.io.in(vicachePortId) <> vicache.io.mem core.io.vimem <> vicache.io.cpu }