From 95de358a9607765c35cf3d775a604f57d4a9f50a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 17 Jan 2014 14:09:30 -0800 Subject: [PATCH] More of the same FPU fix some SP ops followed by DP stores were not working because they were encoded as subnormals, not NaNs. --- rocket/src/main/scala/fpu.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index ed9d537f..15c3f83f 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -464,7 +464,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val load_wb_tag = RegEnable(io.dpath.dmem_resp_tag, io.dpath.dmem_resp_val) val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9) val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12) - val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1), rec_s), rec_d) + val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1, 32), rec_s), rec_d) // regfile val regfile = Mem(Bits(width = 65), 32) @@ -526,7 +526,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits.data, fpmu.io.out.bits.exc), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits.data, ifpu.io.out.bits.exc), - Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, sfma.io.out, sfma.io.exc), + Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, Cat(SInt(-1, 32), sfma.io.out), sfma.io.exc), Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out, dfma.io.exc)) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset))