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Add RISC-V instruction disassembler

This commit is contained in:
Andrew Waterman
2013-06-13 10:31:04 -07:00
parent 569d8fd796
commit 95c5147dc5
3 changed files with 644 additions and 256 deletions

View File

@ -1,6 +1,7 @@
package rocket
import Chisel._
import scala.math._
object Util
{
@ -24,6 +25,77 @@ object AVec
tabulate(n1)(i1 => tabulate(n2)(f(i1, _)))
}
object Str
{
def apply(s: String): Bits = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
Lit(i, s.length*8){Bits()}
}
def apply(x: Char): Bits = {
require(validChar(x))
Lit(x, 8){Bits()}
}
def apply(x: UFix): Bits = apply(x, 10)
def apply(x: UFix, radix: Int): Bits = {
val rad = UFix(radix)
val digs = digits(radix)
val w = x.getWidth
require(w > 0)
var q = x
var s = digs(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux(Bool(radix == 10) && q === UFix(0), Str(' '), digs(q % rad)), s)
}
s
}
def apply(x: Fix): Bits = apply(x, 10)
def apply(x: Fix, radix: Int): Bits = {
val neg = x < Fix(0)
val abs = Mux(neg, -x, x).toUFix
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = UFix(radix)
val digs = digits(radix)
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digs(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === UFix(0)
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digs(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
def bigIntToString(x: BigInt): String = {
val s = new StringBuilder
var b = x
while (b != 0) {
s += (x & 0xFF).toChar
b = b >> 8
}
s.toString
}
private def digit(d: Int): Char = (if (d < 10) '0'+d else 'a'-10+d).toChar
private def digits(radix: Int): Vec[Bits] =
AVec((0 until radix).map(i => Str(digit(i))))
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
// is there a better way to do do this?