riscv/rocket-chip
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Add RISC-V instruction disassembler

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This commit is contained in:
Andrew Waterman
2013-06-13 10:31:04 -07:00
parent 569d8fd796
commit 95c5147dc5
3 changed files with 644 additions and 256 deletions
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12
rocket/src/main/scala/dpath.scala
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@ -196,6 +196,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
val pcr = new PCR
pcr.io.host <> io.host
pcr.io <> io.ctrl
pcr.io.pc := wb_reg_pc
io.ctrl.pcr_replay := pcr.io.replay
io.ptw.ptbr := pcr.io.ptbr
@ -331,9 +332,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec),
wb_reg_pc))).toUFix // PC_WB
// expose debug signals to testbench
// XXX debug() doesn't right, so create a false dependence
val debugList = List(wb_reg_pc, wb_reg_inst, wb_wen, wb_reg_waddr, wb_wdata, wb_reg_rs1, wb_reg_rs2)
pcr.io.pc := wb_reg_pc | (debugList.map(d => d^d).reduce(_|_)).toUFix
debugList.foreach(debug _)
printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] %s\n",
tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc,
Mux(wb_wen, wb_reg_waddr, UFix(0)), wb_wdata,
wb_reg_inst(26,22), wb_reg_rs1,
wb_reg_inst(21,17), wb_reg_rs2,
wb_reg_inst, Disassemble(wb_reg_inst))
}