riscv/rocket-chip
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Deanonymize CSRFile's IO bundle

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This commit is contained in:
Andrew Waterman 2014-05-09 19:26:43 -07:00
parent fd5f419eb1
commit 94c1f01ec6
1 changed files with 28 additions and 26 deletions
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10
rocket/src/main/scala/csr.scala
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@ -33,9 +33,7 @@ object CSR
val C = Bits(3,2) val C = Bits(3,2)
} }
class CSRFile(implicit conf: RocketConfiguration) extends Module class CSRFileIO(implicit conf: RocketConfiguration) extends Bundle {
{
val io = new Bundle {
val host = new HTIFIO(conf.tl.ln.nClients) val host = new HTIFIO(conf.tl.ln.nClients)
val rw = new Bundle { val rw = new Bundle {
val addr = UInt(INPUT, 12) val addr = UInt(INPUT, 12)
@ -60,7 +58,11 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ) val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
val rocc = new RoCCInterface().flip val rocc = new RoCCInterface().flip
} }
class CSRFile(implicit conf: RocketConfiguration) extends Module
{
val io = new CSRFileIO
val reg_epc = Reg(Bits(width = conf.as.vaddrBits+1)) val reg_epc = Reg(Bits(width = conf.as.vaddrBits+1))
val reg_badvaddr = Reg(Bits(width = conf.as.vaddrBits)) val reg_badvaddr = Reg(Bits(width = conf.as.vaddrBits))