Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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commit
93f41d3359
@ -41,17 +41,22 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
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val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
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val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
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when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
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when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
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// tlb respones come out a cycle later
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val chosen_vec = dtlbchosen === Bits(DTLB_VEC)
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val chosen_vec = dtlbchosen === Bits(DTLB_VEC)
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val chosen_pf = dtlbchosen === Bits(DTLB_VPF)
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val chosen_pf = dtlbchosen === Bits(DTLB_VPF)
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val chosen_cpu = dtlbchosen === Bits(DTLB_CPU)
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val chosen_cpu = dtlbchosen === Bits(DTLB_CPU)
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// vector prefetch doesn't care about exceptions
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dtlbarb.io.in(DTLB_VEC) <> vu.io.vec_tlb_req
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// and shouldn't cause any anyways
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vu.io.vec_tlb_resp.xcpt_ld := chosen_vec && dtlb.io.cpu_resp.xcpt_ld
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vu.io.vec_tlb_resp.xcpt_ld := chosen_vec && dtlb.io.cpu_resp.xcpt_ld
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vu.io.vec_tlb_resp.xcpt_st := chosen_vec && dtlb.io.cpu_resp.xcpt_st
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vu.io.vec_tlb_resp.xcpt_st := chosen_vec && dtlb.io.cpu_resp.xcpt_st
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vu.io.vec_tlb_resp.miss := chosen_vec && dtlb.io.cpu_resp.miss
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vu.io.vec_tlb_resp.miss := chosen_vec && dtlb.io.cpu_resp.miss
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vu.io.vec_tlb_resp.ppn := dtlb.io.cpu_resp.ppn
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vu.io.vec_tlb_resp.ppn := dtlb.io.cpu_resp.ppn
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// vector prefetch doesn't care about exceptions
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// and shouldn't cause any anyways
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dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req
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vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
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vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
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vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
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vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
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vu.io.vec_pftlb_resp.miss := chosen_pf && dtlb.io.cpu_resp.miss
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vu.io.vec_pftlb_resp.miss := chosen_pf && dtlb.io.cpu_resp.miss
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@ -69,10 +74,6 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
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ctrl.io.xcpt_dtlb_st := chosen_cpu && dtlb.io.cpu_resp.xcpt_st
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ctrl.io.xcpt_dtlb_st := chosen_cpu && dtlb.io.cpu_resp.xcpt_st
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ctrl.io.dtlb_miss := chosen_cpu && dtlb.io.cpu_resp.miss
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ctrl.io.dtlb_miss := chosen_cpu && dtlb.io.cpu_resp.miss
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dtlbarb.io.in(DTLB_VEC) <> vu.io.vec_tlb_req
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dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req
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dtlb.io.cpu_req <> dtlbarb.io.out
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dtlb.io.cpu_req <> dtlbarb.io.out
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}
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}
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else
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else
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