riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

change LLC leaf SRAM size

Browse Source
This commit is contained in:
Yunsup Lee 2013-04-22 11:06:31 -07:00
parent 7f5282d355
commit 93df795e48
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/RocketChip.scala
View File

@ -335,7 +335,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
require(clientEndpoints.length == lnWithHtifConf.nClients) require(clientEndpoints.length == lnWithHtifConf.nClients)
val masterEndpoints = (0 until lnWithHtifConf.nMasters).map(new L2CoherenceAgent(_)(ucWithHtifConf)) val masterEndpoints = (0 until lnWithHtifConf.nMasters).map(new L2CoherenceAgent(_)(ucWithHtifConf))
val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) } val llc_tag_leaf = Mem(512, seqRead = true) { Bits(width = 152) }
val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) } val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf) val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
//val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES) //val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)