From 93ca555c20f86660d667bebd1a45dd45583b1d3b Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 2 Mar 2017 13:33:05 -0800
Subject: [PATCH] IntXing: support configurable sync depth

---
 src/main/scala/uncore/tilelink2/IntNodes.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala
index eb241918..77aa2e3b 100644
--- a/src/main/scala/uncore/tilelink2/IntNodes.scala
+++ b/src/main/scala/uncore/tilelink2/IntNodes.scala
@@ -127,7 +127,7 @@ class IntXbar()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class IntXing()(implicit p: Parameters) extends LazyModule
+class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
 {
   val intnode = IntIdentityNode()
 
@@ -138,7 +138,7 @@ class IntXing()(implicit p: Parameters) extends LazyModule
     }
 
     (io.in zip io.out) foreach { case (in, out) =>
-      out := RegNext(RegNext(RegNext(in)))
+      out := (0 to sync).foldLeft(in) { case (a, _) => RegNext(a) }
     }
   }
 }