riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227)

Browse Source
This commit is contained in:
Henry Cook 2016-08-25 17:26:28 -07:00 committed by GitHub
parent 4f388add67
commit 93c801f598
4 changed files with 66 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
emulator/Makefrag-verilator
View File

@ -11,13 +11,11 @@ verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img) $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir)" cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(PROJECT) $(CONFIG)"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img) $(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)" cd $(base_dir) && $(SBT) "run $(generated_dir_debug) $(PROJECT) $(MODEL) $(PROJECT) $(CONFIG)"
mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
%.v: %.fir $(FIRRTL_JAR) %.v: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@) mkdir -p $(dir $@)

17
src/main/scala/coreplex/Testing.scala
View File

@ -66,7 +66,7 @@ object TestGeneration {
def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) } def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
def generateMakefrag(topModuleName: String, configClassName: String) { def generateMakefrag: String = {
def gen(kind: String, s: Seq[RocketTestSuite]) = { def gen(kind: String, s: Seq[RocketTestSuite]) = {
if(s.length > 0) { if(s.length > 0) {
val envs = s.groupBy(_.envName) val envs = s.groupBy(_.envName)
@ -93,18 +93,13 @@ run-$kind-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets)
} else { "\n" } } else { "\n" }
} }
val f = createOutputFile(s"$topModuleName.$configClassName.d") List(
f.write( gen("asm", asmSuites.values.toSeq),
List( gen("bmark", bmarkSuites.values.toSeq),
gen("asm", asmSuites.values.toSeq), gen("regression", regressionSuites.values.toSeq)
gen("bmark", bmarkSuites.values.toSeq), ).mkString("\n")
gen("regression", regressionSuites.values.toSeq)
).mkString("\n"))
f.close
} }
def createOutputFile(name: String) =
new java.io.FileWriter(s"${Driver.targetDir}/$name")
} }
object DefaultTestSuites { object DefaultTestSuites {

112
src/main/scala/rocketchip/Generator.scala
View File

@ -4,81 +4,83 @@ package rocketchip
import Chisel._ import Chisel._
import scala.collection.mutable.{LinkedHashSet,LinkedHashMap} import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
import cde.{Parameters, ParameterDump, Config, Field, CDEMatchError, World} import cde._
import coreplex._ import coreplex._
import java.io.{File, FileWriter}
object GeneratorUtils { case class ParsedInputNames(
def getConfig(projectName: String, configClassName: String): Config = { targetDir: String,
val aggregateConfigs = configClassName.split('_') topProject: String,
topModuleClass: String,
configProject: String,
configs: String) {
val configClasses: Seq[String] = configs.split('_')
val fullConfigClasses: Seq[String] = configClasses.map(configProject + "." + _)
val fullTopModuleClass: String = topProject + "." + topModuleClass
}
aggregateConfigs.foldRight(new Config()) { case (currentConfigName, finalConfig) => trait HasGeneratorUtilities {
def getConfig(names: ParsedInputNames): Config = {
names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) =>
val currentConfig = try { val currentConfig = try {
Class.forName(s"$projectName.$currentConfigName").newInstance.asInstanceOf[Config] Class.forName(currentName).newInstance.asInstanceOf[Config]
} catch { } catch {
case e: java.lang.ClassNotFoundException => case e: java.lang.ClassNotFoundException =>
throwException("Unable to find part \"" + currentConfigName + throwException(s"""Unable to find part "$currentName" from "${names.configs}", did you misspell it?""", e)
"\" of configClassName \"" + configClassName +
"\", did you misspell it?", e)
} }
currentConfig ++ finalConfig currentConfig ++ config
} }
} }
def getParameters(config: Config): Parameters = def getParameters(names: ParsedInputNames): Parameters = getParameters(getConfig(names))
Parameters.root(config.toInstance)
def getParameters(projectName: String, configClassName: String): Parameters = def getParameters(config: Config): Parameters = Parameters.root(config.toInstance)
getParameters(getConfig(projectName, configClassName))
def elaborate(fullName: String, args: Array[String], params: Parameters) { import chisel3.internal.firrtl.Circuit
def elaborate(names: ParsedInputNames, params: Parameters): Circuit = {
val gen = () => val gen = () =>
Class.forName(fullName) Class.forName(names.fullTopModuleClass)
.getConstructor(classOf[cde.Parameters]) .getConstructor(classOf[cde.Parameters])
.newInstance(params) .newInstance(params)
.asInstanceOf[Module] .asInstanceOf[Module]
chiselMain.run(args, gen) Driver.elaborate(gen)
} }
def dumpParameters(fname: String) { def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
val pdFile = TestGeneration.createOutputFile(fname) val f = new File(targetDir, fname)
pdFile.write(ParameterDump.getDump) val fw = new FileWriter(f)
pdFile.close fw.write(contents)
} fw.close
f
def dumpKnobs(configClassName: String, world: World) {
val knbFile = TestGeneration.createOutputFile(configClassName + ".knb")
knbFile.write(world.getKnobs)
knbFile.close
val cstFile = TestGeneration.createOutputFile(configClassName + ".cst")
cstFile.write(world.getConstraints)
cstFile.close
}
def dumpConfigString(fname: String, params: Parameters) {
val cfgFile = new java.io.FileOutputStream(Driver.targetDir + "/" + fname)
cfgFile.write(params(ConfigString))
cfgFile.close
} }
} }
import GeneratorUtils._
object RocketChipGenerator extends App { trait Generator extends App with HasGeneratorUtilities {
val projectName = args(0) lazy val names = {
val topModuleName = args(1) require(args.size == 5, "Usage: sbt> " +
val configClassName = args(2) "run TargetDir TopModuleProjectName TopModuleName ConfigProjectName ConfigNameString")
ParsedInputNames(
val config = getConfig(projectName, configClassName) targetDir = args(0),
val world = config.toInstance topProject = args(1),
val paramsFromConfig = Parameters.root(world) topModuleClass = args(2),
configProject = args(3),
elaborate(s"$projectName.$topModuleName", args.drop(3), paramsFromConfig) configs = args(4))
}
TestGeneration.addSuite(new RegressionTestSuite(paramsFromConfig(RegressionTestNames))) lazy val config = getConfig(names)
TestGeneration.generateMakefrag(topModuleName, configClassName) lazy val world = config.toInstance
lazy val params = Parameters.root(world)
dumpParameters(s"$topModuleName.$configClassName.prm") lazy val circuit = elaborate(names, params)
dumpKnobs(configClassName, world) }
dumpConfigString(s"$configClassName.cfg", paramsFromConfig)
object RocketChipGenerator extends Generator {
val longName = names.topModuleClass + "." + names.configs
val td = names.targetDir
Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites
writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
writeOutputFile(td, s"${names.configs}.cfg", params(ConfigString).toString) // String for software
} }

3
vsim/Makefrag-verilog
View File

@ -7,8 +7,7 @@
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img) $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(notdir $*) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem" cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(PROJECT) $(CONFIG)"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR) $(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@) mkdir -p $(dir $@)