riscv/rocket-chip
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Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227)

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This commit is contained in:
Henry Cook
2016-08-25 17:26:28 -07:00
committed by GitHub
parent 4f388add67
commit 93c801f598
4 changed files with 66 additions and 72 deletions
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vsim/Makefrag-verilog
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@ -7,8 +7,7 @@
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(notdir $*) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(PROJECT) $(CONFIG)"
$(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)