riscv/rocket-chip
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Artefact output (#545)

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* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
This commit is contained in:
Wesley W. Terpstra 2017-02-02 19:24:55 -08:00 committed by GitHub
parent 094b3bc2b1
commit 93b2fa197e
10 changed files with 25 additions and 69 deletions
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21
Makefrag
View File

@ -53,26 +53,5 @@ bootrom_img = $(base_dir)/bootrom/bootrom.img
%.riscv.hex: %.riscv
$(MAKE) -C $(dir $@) $(notdir $@)
#---------------------------------------------------------------------
# Constants Header Files
#---------------------------------------------------------------------
# sed uses -E (instead of -r) for BSD support
params_file = $(generated_dir)/$(long_name).prm
consts_header = $(generated_dir)/consts.$(CONFIG).h
$(consts_header): $(params_file)
echo "#ifndef __CONST_H__" > $@
echo "#define __CONST_H__" >> $@
sed -E 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
echo "#endif // __CONST_H__" >> $@
params_file_debug = $(generated_dir_debug)/$(long_name).prm
consts_header_debug = $(generated_dir_debug)/consts.$(CONFIG).h
$(consts_header_debug): $(params_file_debug)
echo "#ifndef __CONST_H__" > $@
echo "#define __CONST_H__" >> $@
sed -E 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
echo "#endif // __CONST_H__" >> $@
clean-run-output:
rm -f $(output_dir)/{*.out,*.run,*.vpd}

12
emulator/Makefrag-verilator
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@ -8,11 +8,11 @@ verilog_debug = $(generated_dir_debug)/$(long_name).v
.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
@ -64,16 +64,16 @@ headers = $(wildcard $(base_dir)/csrc/*.h)
model_header = $(generated_dir)/$(long_name)/V$(MODEL).h
model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
$(emu): $(verilog) $(cppfiles) $(headers) $(consts_header) $(INSTALLED_VERILATOR)
$(emu): $(verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
-CFLAGS "-I$(generated_dir) -include $(model_header)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)"
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk

6
src/main/scala/coreplex/RISCVPlatform.scala
View File

@ -31,9 +31,7 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
lazy val configString = {
val managers = l1tol2.node.edgesIn(0).manager.managers
// Use the existing config string if the user overrode it
ConfigStringOutput.contents.getOrElse(
rocketchip.GenerateConfigString(p, clint, plic, managers))
rocketchip.GenerateConfigString(p, clint, plic, managers)
}
}
@ -58,5 +56,5 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast)))
println(s"\nGenerated Configuration String\n${outer.configString}")
ConfigStringOutput.contents = Some(outer.configString)
ElaborationArtefacts.add("cfg", outer.configString)
}

3
src/main/scala/groundtest/Generator.scala
View File

@ -5,7 +5,6 @@ package groundtest
object Generator extends util.GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateGraphML
generateTestSuiteMakefrags // TODO: Needed only for legacy make targets
generateParameterDump // TODO: Needed only for legacy make targets
generateArtefacts
}

2
src/main/scala/rocketchip/BaseTop.scala
View File

@ -13,7 +13,7 @@ import util._
import rocket._
abstract class BareTop(implicit p: Parameters) extends LazyModule {
TopModule.contents = Some(this)
ElaborationArtefacts.add("graphml", graphML)
}
abstract class BareTopBundle[+L <: BareTop](_outer: L) extends GenericParameterizedBundle(_outer) {

4
src/main/scala/rocketchip/Generator.scala
View File

@ -77,7 +77,5 @@ object Generator extends util.GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateTestSuiteMakefrags
generateConfigString
generateGraphML
generateParameterDump
generateArtefacts
}

3
src/main/scala/unittest/Generator.scala
View File

@ -5,7 +5,6 @@ package unittest
object Generator extends util.GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateGraphML
generateTestSuiteMakefrags // TODO: Needed only for legacy make targets
generateParameterDump // TODO: Needed only for legacy make targets
generateArtefacts
}

27
src/main/scala/util/GeneratorUtils.scala
View File

@ -103,26 +103,17 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
TestGeneration.addSuite(DefaultTestSuites.singleRegression)
}
/** Output a global Parameter dump, which an external script can turn into Verilog headers. */
def generateParameterDump {
writeOutputFile(td, s"$longName.prm", "")
/** Output files created as a side-effect of elaboration */
def generateArtefacts {
ElaborationArtefacts.files.foreach { case (extension, contents) =>
writeOutputFile(td, s"${names.configs}.${extension}", contents ())
}
/** Output a global ConfigString, for use by the RISC-V software ecosystem. */
def generateConfigString {
ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c))
}
/** Output a global LazyModule topology for documentation purposes. */
def generateGraphML {
TopModule.contents.foreach(lm => writeOutputFile(td, s"${names.configs}.graphml", lm.graphML))
}
}
object ConfigStringOutput {
var contents: Option[String] = None
}
object TopModule {
var contents: Option[LazyModule] = None
object ElaborationArtefacts {
var files: Seq[(String, () => String)] = Nil
def add(extension: String, contents: => String) {
files = (extension, () => contents) +: files
}
}

6
vsim/Makefrag
View File

@ -11,7 +11,6 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
sim_vsrcs = \
$(generated_dir)/$(long_name).v \
$(generated_dir)/$(long_name).behav_srams.v \
$(generated_dir)/consts.$(CONFIG).vh \
$(base_dir)/vsrc/$(TB).v \
$(base_dir)/vsrc/SimDTM.v \
$(bb_vsrcs)
@ -42,7 +41,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
-CC "-I$(RISCV)/include" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
-CC "-include $(consts_header)" \
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
@ -65,14 +63,14 @@ VCS_OPTS += -CC "-DVCS_VPI"
#--------------------------------------------------------------------
simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
$(simv) : $(sim_vsrcs) $(sim_csrcs)
cd $(sim_dir) && \
rm -rf csrc && \
$(VCS) $(VCS_OPTS) -o $(simv) \
-debug_pp \
simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
cd $(sim_dir) && \
rm -rf csrc && \
$(VCS) $(VCS_OPTS) -o $(simv_debug) \

8
vsim/Makefrag-verilog
View File

@ -8,7 +8,7 @@ verilog = $(generated_dir)/$(long_name).v
# files.
.SECONDARY: $(firrtl) $(verilog)
$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
@ -22,12 +22,6 @@ $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf
$(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
mv $@.tmp $@
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(long_name).prm
echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
echo "\`endif // CONST_VH" >> $@
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------