riscv/rocket-chip
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Artefact output (#545)

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* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
This commit is contained in:
Wesley W. Terpstra
2017-02-02 19:24:55 -08:00
committed by GitHub
parent 094b3bc2b1
commit 93b2fa197e
10 changed files with 25 additions and 69 deletions
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8
vsim/Makefrag-verilog
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@ -8,7 +8,7 @@ verilog = $(generated_dir)/$(long_name).v
# files.
.SECONDARY: $(firrtl) $(verilog)
$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
@ -22,12 +22,6 @@ $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf
$(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
mv $@.tmp $@
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(long_name).prm
echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
echo "\`endif // CONST_VH" >> $@
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------