riscv/rocket-chip
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Artefact output (#545)

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* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
This commit is contained in:
Wesley W. Terpstra
2017-02-02 19:24:55 -08:00
committed by GitHub
parent 094b3bc2b1
commit 93b2fa197e
10 changed files with 25 additions and 69 deletions
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6
vsim/Makefrag
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@ -11,7 +11,6 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
sim_vsrcs = \
$(generated_dir)/$(long_name).v \
$(generated_dir)/$(long_name).behav_srams.v \
$(generated_dir)/consts.$(CONFIG).vh \
$(base_dir)/vsrc/$(TB).v \
$(base_dir)/vsrc/SimDTM.v \
$(bb_vsrcs)
@ -42,7 +41,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
-CC "-I$(RISCV)/include" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
-CC "-include $(consts_header)" \
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
@ -65,14 +63,14 @@ VCS_OPTS += -CC "-DVCS_VPI"
#--------------------------------------------------------------------
simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
$(simv) : $(sim_vsrcs) $(sim_csrcs)
cd $(sim_dir) && \
rm -rf csrc && \
$(VCS) $(VCS_OPTS) -o $(simv) \
-debug_pp \
simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
cd $(sim_dir) && \
rm -rf csrc && \
$(VCS) $(VCS_OPTS) -o $(simv_debug) \