riscv/rocket-chip
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Artefact output (#545)

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* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
This commit is contained in:
Wesley W. Terpstra
2017-02-02 19:24:55 -08:00
committed by GitHub
parent 094b3bc2b1
commit 93b2fa197e
10 changed files with 25 additions and 69 deletions
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12
emulator/Makefrag-verilator
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@ -8,11 +8,11 @@ verilog_debug = $(generated_dir_debug)/$(long_name).v
.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
@ -64,16 +64,16 @@ headers = $(wildcard $(base_dir)/csrc/*.h)
model_header = $(generated_dir)/$(long_name)/V$(MODEL).h
model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
$(emu): $(verilog) $(cppfiles) $(headers) $(consts_header) $(INSTALLED_VERILATOR)
$(emu): $(verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
-CFLAGS "-I$(generated_dir) -include $(model_header)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)"
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk