everything to get emulator working
This commit is contained in:
Huy Vo
218
csrc/emulator.cc
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218
csrc/emulator.cc
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@ -0,0 +1,218 @@
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#include "htif_phy.h"
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <map>
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#include "common.h"
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#include "emulator.h"
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#include "mm_emulator.cc"
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#include "Top.h" // chisel-generated code...
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#include "disasm.h"
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int main(int argc, char** argv)
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{
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int fromhost_fd = -1, tohost_fd = -1;
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unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
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uint64_t max_cycles = 0;
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uint64_t trace_count = 0;
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int start = 0;
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bool log = false;
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bool quiet = false;
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const char* vcd = NULL;
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const char* loadmem = NULL;
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FILE *vcdfile = NULL, *logfile = stderr;
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const char* failure = NULL;
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// for disassembly
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disassembler disasm;
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char if_inst_str[1024];
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char id_inst_str[1024];
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char ex_inst_str[1024];
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char mem_inst_str[1024];
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char wb_inst_str[1024];
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// used to register values from EX stage for trace
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uint64_t mem_reg_raddr1 = 0, mem_reg_raddr2 = 0;
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uint64_t wb_reg_raddr1 = 0, wb_reg_raddr2 = 0;
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uint64_t mem_reg_rs1 = 0, mem_reg_rs2 = 0, mem_reg_inst = 0, ex_reg_inst = 0;
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uint64_t wb_reg_rs1 = 0, wb_reg_rs2 = 0, wb_reg_inst = 0;
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uint64_t id_icache_miss = 0, if_icache_req = 0, id_itlb_miss = 0;
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for (int i = 1; i < argc; i++)
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{
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std::string arg = argv[i];
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if (arg == "-l")
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log = true;
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else if (arg == "-q")
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quiet = true;
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else if (arg.substr(0, 2) == "-v")
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vcd = argv[i]+2;
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else if (arg.substr(0, 2) == "-m")
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max_cycles = atoll(argv[i]+2);
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else if (arg.substr(0, 2) == "-s")
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random_seed = atoi(argv[i]+2);
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else if (arg.substr(0, 10) == "+fromhost=")
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fromhost_fd = atoi(argv[i]+10);
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else if (arg.substr(0, 8) == "+tohost=")
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tohost_fd = atoi(argv[i]+8);
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else if (arg.substr(0, 9) == "+loadmem=")
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loadmem = argv[i]+9;
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else
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{
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fprintf(stderr, "unknown option: %s\n", argv[i]);
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exit(1);
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}
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}
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demand(fcntl(fromhost_fd,F_GETFD) >= 0, "fromhost file not open");
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demand(fcntl(tohost_fd,F_GETFD) >= 0, "tohost file not open");
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if (vcd)
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{
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// Create a VCD file
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vcdfile = strcmp(vcd, "-") == 0 ? stdout : fopen(vcd, "w");
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assert(vcdfile);
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fprintf(vcdfile, "$scope module Testbench $end\n");
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fprintf(vcdfile, "$var reg 256 NDISASM_IF if_instruction $end\n");
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fprintf(vcdfile, "$var reg 256 NDISASM_ID id_instruction $end\n");
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fprintf(vcdfile, "$var reg 256 NDISASM_EX ex_instruction $end\n");
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fprintf(vcdfile, "$var reg 256 NDISASM_MEM mem_instruction $end\n");
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fprintf(vcdfile, "$var reg 16 NCYCLE cycle $end\n");
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fprintf(vcdfile, "$upscope $end\n");
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}
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// basic fixed latency memory model
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uint64_t* mem = mm_init();
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if (loadmem != NULL)
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load_mem(mem, loadmem);
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// The chisel generated code
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Top_t tile;
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srand(random_seed);
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tile.init(random_seed != 0);
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// reset for a few cycles to support pipelined reset
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tile.Top__io_host_in_valid = LIT<1>(0);
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tile.Top__io_host_out_ready = LIT<1>(0);
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for (int i = 0; i < 10; i++)
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{
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tile.clock_lo(LIT<1>(1));
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tile.clock_hi(LIT<1>(1));
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}
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htif_phy_t htif_phy(tile.Top__io_host_in_bits.width(), fromhost_fd, tohost_fd);
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while (max_cycles == 0 || trace_count < max_cycles)
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{
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// memory model
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mm_tick_emulator (
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tile.Top__io_mem_req_cmd_valid.lo_word(),
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&tile.Top__io_mem_req_cmd_ready.values[0],
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tile.Top__io_mem_req_cmd_bits_rw.lo_word(),
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tile.Top__io_mem_req_cmd_bits_addr.lo_word(),
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tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
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tile.Top__io_mem_req_data_valid.lo_word(),
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&tile.Top__io_mem_req_data_ready.values[0],
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&tile.Top__io_mem_req_data_bits_data.values[0],
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&tile.Top__io_mem_resp_valid.values[0],
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&tile.Top__io_mem_resp_bits_tag.values[0],
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&tile.Top__io_mem_resp_bits_data.values[0]
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);
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tile.Top__io_host_in_valid = LIT<1>(htif_phy.in_valid());
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tile.Top__io_host_in_bits = LIT<64>(htif_phy.in_bits());
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tile.Top__io_host_out_ready = LIT<1>(htif_phy.out_ready());
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tile.clock_lo(LIT<1>(0));
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htif_phy.tick(tile.Top__io_host_in_ready.lo_word(),
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tile.Top__io_host_out_valid.lo_word(),
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tile.Top__io_host_out_bits.lo_word());
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if (tile.Top__io_debug_error_mode.lo_word())
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{
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failure = "entered error mode";
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break;
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}
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if (log || (quiet && trace_count % 10000 == 0))
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{
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insn_t insn;
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insn.bits = wb_reg_inst;
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strcpy(wb_inst_str, disasm.disassemble(insn).c_str());
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fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
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(long long)trace_count, tile.Top_Tile_cpu_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_cpu_dpath__wb_reg_pc.lo_word(), \
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tile.Top_Tile_cpu_dpath_rfile__io_w0_addr.lo_word(), tile.Top_Tile_cpu_dpath_rfile__io_w0_data.lo_word(), tile.Top_Tile_cpu_dpath_rfile__io_w0_en.lo_word(),
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wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_inst_str);
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}
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if (vcd)
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{
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tile.dump(vcdfile, trace_count); // dump all signals to vcd
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#define dump_disasm(inst, name) do { \
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insn_t insn; \
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insn.bits = inst; \
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std::string dasm = disasm.disassemble(insn); \
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int namelen = strlen(name), pos = 0; \
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char str[1 + dasm.length()*8 + 1 + namelen + 1 + 1]; \
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str[pos++] = 'b'; \
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for (size_t i = 0; i < dasm.length()*8; i++) \
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str[pos++] = ((dasm[i/8] >> (7-(i%8))) & 1) + '0'; \
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str[pos++] = ' '; \
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memcpy(str + pos, name, namelen); pos += namelen; \
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str[pos++] = '\n'; \
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str[pos] = 0; \
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fputs(str, vcdfile); \
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} while(0)
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dump_disasm(tile.Top_Tile_cpu_dpath__id_reg_inst_shadow.lo_word(), "NDISASM_IF");
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dump_disasm(tile.Top_Tile_cpu_dpath__id_reg_inst.lo_word(), "NDISASM_ID");
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dump_disasm(ex_reg_inst, "NDISASM_EX");
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dump_disasm(mem_reg_inst, "NDISASM_MEM");
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dat_dump(vcdfile, dat_t<64>(trace_count), "NCYCLE\n");
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}
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// delay values from ex stage for trace output on the following cycle
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wb_reg_inst = mem_reg_inst;
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wb_reg_raddr1 = mem_reg_raddr1;
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wb_reg_raddr2 = mem_reg_raddr2;
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wb_reg_rs1 = mem_reg_rs1;
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wb_reg_rs2 = mem_reg_rs2;
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mem_reg_inst = ex_reg_inst;
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mem_reg_raddr1 = (mem_reg_inst >> 22) & 0x1f;
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mem_reg_raddr2 = (mem_reg_inst >> 17) & 0x1f;
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mem_reg_rs1 = tile.Top_Tile_cpu_dpath__ex_reg_rs1.lo_word();
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mem_reg_rs2 = tile.Top_Tile_cpu_dpath__ex_reg_rs2.lo_word();
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ex_reg_inst = tile.Top_Tile_cpu_dpath__id_reg_inst.lo_word();
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tile.clock_hi(LIT<1>(0));
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trace_count++;
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if (trace_count == max_cycles)
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{
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failure = "timeout";
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break;
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}
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}
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if (vcd)
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fclose(vcdfile);
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if (failure)
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{
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fprintf(logfile, "*** FAILED *** (%s) after %lld cycles\n", failure, (long long)trace_count);
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return -1;
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}
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close(tohost_fd);
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close(fromhost_fd);
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return 0;
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}
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112
csrc/vcs_main.cc
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112
csrc/vcs_main.cc
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@ -0,0 +1,112 @@
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#include "mm_model.h"
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#include "htif_phy.h"
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#include "mm_types.h"
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#include "mm_emulator.cc"
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#include <DirectC.h>
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htif_phy_t* htif_phy = NULL;
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extern "C" {
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void memory_tick(
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vc_handle mem_req_val,
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vc_handle mem_req_rdy,
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vc_handle mem_req_store,
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vc_handle mem_req_addr,
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vc_handle mem_req_tag,
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vc_handle mem_req_data_val,
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vc_handle mem_req_data_rdy,
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vc_handle mem_req_data_bits,
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vc_handle mem_resp_val,
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vc_handle mem_resp_tag,
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vc_handle mem_resp_data)
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{
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uint64_t req_data[MM_WORD_SIZE*refill_size/sizeof(uint64_t)];
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for (size_t i = 0; i < MM_WORD_SIZE*refill_size/sizeof(uint32_t); i++)
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((uint32_t*)req_data)[i] = vc_4stVectorRef(mem_req_data_bits)[i].d;
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uint64_t req_rdy, req_data_rdy, resp_val, resp_tag;
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uint64_t resp_data[MM_WORD_SIZE*refill_size/sizeof(uint64_t)];
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mm_tick_emulator(
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vc_getScalar(mem_req_val),
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&req_rdy,
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vc_getScalar(mem_req_store),
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vc_4stVectorRef(mem_req_addr)->d,
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vc_4stVectorRef(mem_req_tag)->d,
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vc_getScalar(mem_req_data_val),
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&req_data_rdy,
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req_data,
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&resp_val,
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&resp_tag,
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resp_data
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);
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vc_putScalar(mem_req_rdy, req_rdy);
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vc_putScalar(mem_req_data_rdy, req_data_rdy);
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vc_putScalar(mem_resp_val, resp_val);
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vec32 t;
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t.c = 0;
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t.d = resp_tag;
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vc_put4stVector(mem_resp_tag, &t);
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vec32 d[MM_WORD_SIZE*refill_size/sizeof(uint32_t)];
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for (size_t i = 0; i < MM_WORD_SIZE*refill_size/sizeof(uint32_t); i++)
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{
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d[i].c = 0;
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d[i].d = ((uint32_t*)resp_data)[i];
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}
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vc_put4stVector(mem_resp_data, d);
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}
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void htif_init
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(
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vc_handle fromhost,
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vc_handle tohost,
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vc_handle width,
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vc_handle loadmem
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)
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{
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uint64_t* mem = mm_init();
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vec32* fh = vc_4stVectorRef(fromhost);
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vec32* th = vc_4stVectorRef(tohost);
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vec32* w = vc_4stVectorRef(width);
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char loadmem_str[1024];
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vc_VectorToString(loadmem, loadmem_str);
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if (*loadmem_str)
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load_mem(mem, loadmem_str);
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assert(w->d <= 32); // htif_tick assumes data fits in a vec32
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htif_phy = new htif_phy_t(w->d, fh->d, th->d);
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}
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void htif_tick
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(
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vc_handle htif_in_valid,
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vc_handle htif_in_ready,
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vc_handle htif_in_bits,
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vc_handle htif_out_valid,
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vc_handle htif_out_ready,
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vc_handle htif_out_bits
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)
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{
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vec32* ob = vc_4stVectorRef(htif_out_bits);
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htif_phy->tick(vc_getScalar(htif_in_ready), vc_getScalar(htif_out_valid), ob->d);
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vc_putScalar(htif_in_valid, htif_phy->in_valid());
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vc_putScalar(htif_out_ready, htif_phy->out_ready());
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vec32 ib;
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ib.c = 0;
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ib.d = htif_phy->in_bits();
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vc_put4stVector(htif_in_bits, &ib);
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}
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}
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