From 938effc053a583df2c8d94e345812b3d6d26c044 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 22 Jul 2012 21:05:52 -0700 Subject: [PATCH] don't dequeue probe queue during reset --- rocket/src/main/scala/nbdcache.scala | 5 +++-- rocket/src/main/scala/uncore.scala | 9 +++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index c9a172a2..c63e3696 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -495,8 +495,8 @@ class ProbeUnit(co: CoherencePolicy) extends Component { val address = Bits(OUTPUT, PADDR_BITS-OFFSET_BITS) } - val s_invalid :: s_meta_req :: s_meta_resp :: s_mshr_req :: s_probe_rep :: s_writeback_req :: s_writeback_resp :: Nil = Enum(7) { UFix() } - val state = Reg(resetVal = s_invalid) + val s_reset :: s_invalid :: s_meta_req :: s_meta_resp :: s_mshr_req :: s_probe_rep :: s_writeback_req :: s_writeback_resp :: Nil = Enum(8) { UFix() } + val state = Reg(resetVal = s_reset) val line_state = Reg() { UFix() } val way_oh = Reg() { Bits() } val req = Reg() { new ProbeRequest() } @@ -526,6 +526,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component { state := s_meta_req req := io.req.bits } + when (state === s_reset) { state := s_invalid } io.req.ready := state === s_invalid io.rep.valid := state === s_probe_rep && io.meta_req.ready diff --git a/rocket/src/main/scala/uncore.scala b/rocket/src/main/scala/uncore.scala index ead75252..6ea359ce 100644 --- a/rocket/src/main/scala/uncore.scala +++ b/rocket/src/main/scala/uncore.scala @@ -140,6 +140,8 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component { val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val mem_cnt_next = mem_cnt + UFix(1) val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) + val p_req_initial_flags = Bits(width = ntiles) + p_req_initial_flags := ~(io.tile_incoherent | UFixToOH(io.alloc_req.bits.tile_id(log2Up(ntiles)-1,0))) //TODO: Broadcast only io.busy := state != s_idle io.addr := addr_ @@ -178,15 +180,14 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component { tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init) x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0)) - val p_req_initial_flags = ~(io.tile_incoherent | UFixToOH(io.alloc_req.bits.tile_id)) //TODO: Broadcast only - p_req_flags := p_req_initial_flags(ntiles-1,0) + p_req_flags := p_req_initial_flags mem_cnt := UFix(0) p_w_mem_cmd_sent := Bool(false) x_w_mem_cmd_sent := Bool(false) io.pop_x_init := UFix(1) << io.alloc_req.bits.tile_id if(ntiles > 1) { - p_rep_count := UFix(ntiles-1) - state := Mux(p_req_initial_flags(ntiles-1,0).orR, s_probe, s_mem) + p_rep_count := PopCount(p_req_initial_flags) + state := Mux(p_req_initial_flags.orR, s_probe, s_mem) } else state := s_mem } }