riscv/rocket-chip
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ready signal fix

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This commit is contained in:
Henry Cook 2013-01-27 23:04:35 -08:00
parent 409b549d3c
commit 931cffa749
1 changed files with 5 additions and 5 deletions
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10
rocket/src/main/scala/tile.scala
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@ -42,22 +42,22 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
arbiter.io.requestor(1) <> icache.io.mem arbiter.io.requestor(1) <> icache.io.mem
io.tilelink.acquire.valid := arbiter.io.mem.acquire.valid io.tilelink.acquire.valid := arbiter.io.mem.acquire.valid
io.tilelink.acquire.ready := arbiter.io.mem.acquire.ready arbiter.io.mem.acquire.ready := io.tilelink.acquire.ready
io.tilelink.acquire.bits := arbiter.io.mem.acquire.bits io.tilelink.acquire.bits := arbiter.io.mem.acquire.bits
io.tilelink.acquire_data.valid := dcache.io.mem.acquire_data.valid io.tilelink.acquire_data.valid := dcache.io.mem.acquire_data.valid
io.tilelink.acquire_data.ready := dcache.io.mem.acquire_data.ready dcache.io.mem.acquire_data.ready := io.tilelink.acquire_data.ready
io.tilelink.acquire_data.bits := dcache.io.mem.acquire_data.bits io.tilelink.acquire_data.bits := dcache.io.mem.acquire_data.bits
arbiter.io.mem.abort <> io.tilelink.abort arbiter.io.mem.abort <> io.tilelink.abort
arbiter.io.mem.grant <> io.tilelink.grant arbiter.io.mem.grant <> io.tilelink.grant
io.tilelink.grant_ack.valid := arbiter.io.mem.grant_ack.valid io.tilelink.grant_ack.valid := arbiter.io.mem.grant_ack.valid
io.tilelink.grant_ack.ready := arbiter.io.mem.grant_ack.ready arbiter.io.mem.grant_ack.ready := io.tilelink.grant_ack.ready
io.tilelink.grant_ack.bits := arbiter.io.mem.grant_ack.bits io.tilelink.grant_ack.bits := arbiter.io.mem.grant_ack.bits
dcache.io.mem.probe <> io.tilelink.probe dcache.io.mem.probe <> io.tilelink.probe
io.tilelink.release.valid := dcache.io.mem.release.valid io.tilelink.release.valid := dcache.io.mem.release.valid
io.tilelink.release.ready := dcache.io.mem.release.ready dcache.io.mem.release.ready := io.tilelink.release.ready
io.tilelink.release.bits := dcache.io.mem.release.bits io.tilelink.release.bits := dcache.io.mem.release.bits
io.tilelink.release_data.valid := dcache.io.mem.release_data.valid io.tilelink.release_data.valid := dcache.io.mem.release_data.valid
io.tilelink.release_data.ready := dcache.io.mem.release_data.ready dcache.io.mem.release_data.ready := io.tilelink.release_data.ready
io.tilelink.release_data.bits := dcache.io.mem.release_data.bits io.tilelink.release_data.bits := dcache.io.mem.release_data.bits
val ioSubBundles = io.tilelink.getClass.getMethods.filter( x => val ioSubBundles = io.tilelink.getClass.getMethods.filter( x =>