refactor ready/valid logic for routing release messages in the l2
This commit is contained in:
Henry Cook
Howard Mao
parent
f97bd70df5
commit
929d8e31f7
@ -83,19 +83,15 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
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// Handle releases, which might be voluntary and might have data
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val trackerReleaseIOs = trackerList.map(_.io.inner.release)
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val releaseReadys = Vec(trackerReleaseIOs.map(_.ready)).toBits
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val releaseMatches = Vec(trackerList.map(_.io.has_release_match)).toBits
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val release_idx = PriorityEncoder(releaseMatches)
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io.inner.release.ready := releaseReadys(release_idx)
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io.inner.release.ready := releaseReadys.orR
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trackerReleaseIOs.zipWithIndex.foreach {
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case(tracker, i) =>
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tracker.valid := io.inner.release.valid && (release_idx === UInt(i))
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tracker.valid := io.inner.release.valid
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tracker.bits := io.inner.release.bits
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tracker.bits.data := DataQueueLocation(rel_data_cnt,
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(if(i < nReleaseTransactors) inVolWBQueue
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else inClientReleaseQueue)).toBits
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}
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assert(!(io.inner.release.valid && !releaseMatches.orR),
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"Non-voluntary release should always have a Tracker waiting for it.")
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// Wire probe requests and grant reply to clients, finish acks from clients
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// Note that we bypass the Grant data subbundles
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@ -129,85 +125,68 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
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class BroadcastXactTracker(implicit p: Parameters) extends XactTracker()(p) {
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val io = new ManagerXactTrackerIO
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pinAllReadyValidLow(io)
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}
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class BroadcastVoluntaryReleaseTracker(trackerId: Int)
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(implicit p: Parameters) extends BroadcastXactTracker()(p) {
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val s_idle :: s_outer :: s_grant :: s_ack :: Nil = Enum(UInt(), 4)
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val s_idle :: s_busy :: Nil = Enum(UInt(), 2)
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val state = Reg(init=s_idle)
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val xact = Reg(new BufferedReleaseFromSrc()(p.alterPartial({ case TLId => innerTLId })))
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val coh = ManagerMetadata.onReset
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val collect_irel_data = Reg(init=Bool(false))
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val irel_data_valid = Reg(init=Bits(0, width = innerDataBeats))
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val irel_data_done = connectIncomingDataBeatCounter(io.inner.release)
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val (oacq_data_cnt, oacq_data_done) = connectOutgoingDataBeatCounter(io.outer.acquire)
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val pending_irels = Reg(init=Bits(0, width = io.inner.tlDataBeats))
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val pending_writes = Reg(init=Bits(0, width = io.outer.tlDataBeats))
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val pending_ignt = Reg(init=Bool(false))
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io.has_acquire_conflict := Bool(false)
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io.has_release_match := io.irel().isVoluntary()
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io.has_acquire_match := Bool(false)
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val all_pending_done = !(pending_irels.orR || pending_writes.orR || pending_ignt)
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io.outer.acquire.valid := Bool(false)
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io.outer.grant.ready := Bool(false)
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io.inner.acquire.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.grant.valid := Bool(false)
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io.inner.finish.ready := Bool(false)
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io.inner.grant.bits := coh.makeGrant(xact, UInt(trackerId))
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// Accept a voluntary Release (and any further beats of data)
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pending_irels := (pending_irels & dropPendingBitWhenBeatHasData(io.inner.release))
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io.inner.release.ready := ((state === s_idle) && io.irel().isVoluntary()) || pending_irels.orR
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when(io.inner.release.fire()) { xact.data_buffer(io.irel().addr_beat) := io.irel().data }
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// Write the voluntarily written back data to outer memory using an Acquire.PutBlock
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//TODO: Use io.outer.release instead?
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pending_writes := (pending_writes & dropPendingBitWhenBeatHasData(io.outer.acquire)) |
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addPendingBitWhenBeatHasData(io.inner.release)
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val curr_write_beat = PriorityEncoder(pending_writes)
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io.outer.acquire.valid := state === s_busy && pending_writes.orR
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io.outer.acquire.bits := PutBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block,
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addr_beat = oacq_data_cnt,
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data = xact.data_buffer(oacq_data_cnt))
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addr_beat = curr_write_beat,
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data = xact.data_buffer(curr_write_beat))
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(p.alterPartial({ case TLId => outerTLId }))
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when(collect_irel_data) {
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io.inner.release.ready := Bool(true)
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when(io.inner.release.valid) {
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xact.data_buffer(io.irel().addr_beat) := io.irel().data
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irel_data_valid := irel_data_valid.bitSet(io.irel().addr_beat, Bool(true))
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}
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when(irel_data_done) { collect_irel_data := Bool(false) }
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}
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// Send an acknowledgement
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io.inner.grant.valid := state === s_busy && pending_ignt && !pending_irels && io.outer.grant.valid
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io.inner.grant.bits := coh.makeGrant(xact, UInt(trackerId))
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when(io.inner.grant.fire()) { pending_ignt := Bool(false) }
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io.outer.grant.ready := state === s_busy && io.inner.grant.ready
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switch (state) {
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is(s_idle) {
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io.inner.release.ready := Bool(true)
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when( io.inner.release.valid ) {
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// State machine updates and transaction handler metadata intialization
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when(state === s_idle && io.inner.release.fire()) {
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xact := io.irel()
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xact.data_buffer(UInt(0)) := io.irel().data
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collect_irel_data := io.irel().hasMultibeatData()
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irel_data_valid := io.irel().hasData() << io.irel().addr_beat
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state := Mux(io.irel().hasData(), s_outer,
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Mux(io.irel().requiresAck(), s_ack, s_idle))
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}
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}
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is(s_outer) {
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io.outer.acquire.valid := !collect_irel_data || irel_data_valid(oacq_data_cnt)
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when(oacq_data_done) {
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state := s_grant // converted irel to oacq, so expect grant TODO: Mux(xact.requiresAck(), s_grant, s_idle) ?
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}
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}
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is(s_grant) { // Forward the Grant.voluntaryAck
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io.outer.grant.ready := io.inner.grant.ready
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io.inner.grant.valid := io.outer.grant.valid
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when(io.inner.grant.fire()) {
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state := Mux(io.ignt().requiresAck(), s_ack, s_idle)
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}
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}
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is(s_ack) {
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// TODO: This state is unnecessary if no client will ever issue the
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// pending Acquire that caused this writeback until it receives the
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// Grant.voluntaryAck for this writeback
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io.inner.finish.ready := Bool(true)
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when(io.inner.finish.valid) { state := s_idle }
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when(io.irel().hasMultibeatData()) {
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pending_irels := dropPendingBitWhenBeatHasData(io.inner.release)
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}. otherwise {
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pending_irels := UInt(0)
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}
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pending_writes := addPendingBitWhenBeatHasData(io.inner.release)
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pending_ignt := io.irel().requiresAck()
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state := s_busy
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}
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when(state === s_busy && all_pending_done) { state := s_idle }
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// These IOs are used for routing in the parent
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io.has_acquire_match := Bool(false)
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io.has_acquire_conflict := Bool(false)
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// Checks for illegal behavior
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assert(!(state === s_idle && io.inner.release.fire() && !io.irel().isVoluntary()),
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"VoluntaryReleaseTracker accepted Release that wasn't voluntary!")
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}
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class BroadcastAcquireTracker(trackerId: Int)
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@ -247,9 +226,6 @@ class BroadcastAcquireTracker(trackerId: Int)
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!collect_iacq_data
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io.has_acquire_match := xact.conflicts(io.iacq()) &&
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collect_iacq_data
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io.has_release_match := xact.conflicts(io.irel()) &&
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!io.irel().isVoluntary() &&
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(state === s_probe)
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val outerParams = p.alterPartial({ case TLId => outerTLId })
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@ -357,8 +333,9 @@ class BroadcastAcquireTracker(trackerId: Int)
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}
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// Handle releases, which may have data to be written back
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io.inner.release.ready := !io.irel().hasData() || io.outer.acquire.ready
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when(io.inner.release.valid) {
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val matches = xact.conflicts(io.irel()) && !io.irel().isVoluntary()
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io.inner.release.ready := (!io.irel().hasData() || io.outer.acquire.ready) && matches
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when(io.inner.release.valid && matches) {
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when(io.irel().hasData()) {
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io.outer.acquire.valid := Bool(true)
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when(io.outer.acquire.ready) {
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@ -405,15 +405,14 @@ class TSHRFile(implicit p: Parameters) extends L2HellaCacheModule()(p)
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// Wire releases from clients
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val releaseReadys = Vec(trackerAndWbIOs.map(_.inner.release.ready)).toBits
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val releaseMatches = Vec(trackerAndWbIOs.map(_.has_release_match)).toBits
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io.inner.release.ready := (releaseMatches & releaseReadys).orR
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io.inner.release.ready := releaseReadys.orR
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trackerAndWbIOs foreach { tracker =>
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tracker.inner.release.bits := io.inner.release.bits
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tracker.inner.release.valid := io.inner.release.valid && tracker.has_release_match
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tracker.inner.release.valid := io.inner.release.valid
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}
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assert(PopCount(releaseMatches) <= UInt(nReleaseTransactors),
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assert(PopCount(releaseReadys) <= UInt(nReleaseTransactors),
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"At most a single tracker should match for any given Release")
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assert(!(io.inner.release.valid && !releaseMatches.orR),
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assert(!(io.inner.release.valid && !releaseReadys.orR),
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"Non-voluntary release should always have a Tracker waiting for it.")
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// Wire probe requests and grant reply to clients, finish acks from clients
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@ -491,19 +490,6 @@ abstract class L2XactTracker(implicit p: Parameters) extends XactTracker()(p)
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val isPartial = a.wmask() =/= Acquire.fullWriteMask
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addPendingBitWhenBeat(in.fire() && isPartial && Bool(ignoresWriteMask), a)
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}
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def pinAllReadyValidLow[T <: Data](b: Bundle) {
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b.elements.foreach {
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_._2 match {
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case d: DecoupledIO[_] =>
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if(d.ready.dir == OUTPUT) d.ready := Bool(false)
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else if(d.valid.dir == OUTPUT) d.valid := Bool(false)
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case v: ValidIO[_] => if(v.valid.dir == OUTPUT) v.valid := Bool(false)
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case b: Bundle => pinAllReadyValidLow(b)
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case _ =>
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}
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}
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}
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}
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class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTracker()(p) {
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@ -528,7 +514,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends
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// Accept a voluntary Release (and any further beats of data)
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pending_irels := (pending_irels & dropPendingBitWhenBeatHasData(io.inner.release))
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io.inner.release.ready := state === s_idle || pending_irels.orR
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io.inner.release.ready := ((state === s_idle) && io.irel().isVoluntary()) || pending_irels.orR
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when(io.inner.release.fire()) { xact.data_buffer(io.irel().addr_beat) := io.irel().data }
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// Begin a transaction by getting the current block metadata
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@ -566,7 +552,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends
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xact_old_meta.coh.outer)
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// State machine updates and transaction handler metadata intialization
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when(state === s_idle && io.inner.release.valid) {
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when(state === s_idle && io.inner.release.fire()) {
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xact := io.irel()
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when(io.irel().hasMultibeatData()) {
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pending_irels := dropPendingBitWhenBeatHasData(io.inner.release)
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@ -587,7 +573,6 @@ class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends
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when(state === s_meta_write && io.meta.write.ready) { state := s_idle }
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// These IOs are used for routing in the parent
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io.has_release_match := io.irel().isVoluntary()
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io.has_acquire_match := Bool(false)
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io.has_acquire_conflict := Bool(false)
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@ -816,7 +801,9 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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// Handle incoming releases from clients, which may reduce sharer counts
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// and/or write back dirty data
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io.inner.release.ready := state === s_inner_probe
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io.inner.release.ready := state === s_inner_probe &&
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io.irel().conflicts(xact_addr_block) &&
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!io.irel().isVoluntary()
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val pending_coh_on_irel = HierarchicalMetadata(
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pending_coh.inner.onRelease(io.irel()), // Drop sharer
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Mux(io.irel().hasData(), // Dirty writeback
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@ -1025,9 +1012,6 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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// These IOs are used for routing in the parent
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val in_same_set = xact_addr_idx === io.iacq().addr_block(idxMSB,idxLSB)
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io.has_release_match := io.irel().conflicts(xact_addr_block) &&
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!io.irel().isVoluntary() &&
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io.inner.release.ready
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io.has_acquire_match := iacq_can_merge || iacq_same_xact
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io.has_acquire_conflict := in_same_set && (state =/= s_idle) && !io.has_acquire_match
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//TODO: relax from in_same_set to xact.conflicts(io.iacq())?
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@ -1083,7 +1067,9 @@ class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTrac
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// and/or write back dirty data
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val inner_coh_on_irel = xact.coh.inner.onRelease(io.irel())
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val outer_coh_on_irel = xact.coh.outer.onHit(M_XWR)
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io.inner.release.ready := state === s_inner_probe || state === s_busy
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io.inner.release.ready := (state === s_inner_probe || state === s_busy) &&
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io.irel().conflicts(xact_addr_block) &&
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!io.irel().isVoluntary()
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when(io.inner.release.fire()) {
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xact.coh.inner := inner_coh_on_irel
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data_buffer(io.inner.release.bits.addr_beat) := io.inner.release.bits.data
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@ -1150,7 +1136,6 @@ class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTrac
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when(state === s_wb_resp ) { state := s_idle }
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// These IOs are used for routing in the parent
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io.has_release_match := io.irel().conflicts(xact_addr_block) && !io.irel().isVoluntary() && io.inner.release.ready
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io.has_acquire_match := Bool(false)
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io.has_acquire_conflict := Bool(false)
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}
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@ -117,7 +117,6 @@ abstract class HierarchicalCoherenceAgent(implicit p: Parameters) extends Cohere
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trait HasTrackerConflictIO extends Bundle {
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val has_acquire_conflict = Bool(OUTPUT)
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val has_acquire_match = Bool(OUTPUT)
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val has_release_match = Bool(OUTPUT)
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}
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class ManagerXactTrackerIO(implicit p: Parameters) extends ManagerTLIO()(p)
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@ -154,4 +153,17 @@ abstract class XactTracker(implicit p: Parameters) extends CoherenceAgentModule(
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def dropPendingBitAtDest(in: DecoupledIO[ProbeToDst]): UInt =
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~Fill(in.bits.tlNCachingClients, in.fire()) | ~UIntToOH(in.bits.client_id)
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def pinAllReadyValidLow[T <: Data](b: Bundle) {
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b.elements.foreach {
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_._2 match {
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case d: DecoupledIO[_] =>
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if(d.ready.dir == OUTPUT) d.ready := Bool(false)
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else if(d.valid.dir == OUTPUT) d.valid := Bool(false)
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case v: ValidIO[_] => if(v.valid.dir == OUTPUT) v.valid := Bool(false)
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case b: Bundle => pinAllReadyValidLow(b)
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case _ =>
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}
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}
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}
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}
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