riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

refactor ready/valid logic for routing release messages in the l2

Browse Source
This commit is contained in:
Henry Cook
2016-02-10 11:12:43 -08:00
committed by Howard Mao
parent f97bd70df5
commit 929d8e31f7
3 changed files with 71 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
uncore/src/main/scala/uncore.scala
View File

@ -117,7 +117,6 @@ abstract class HierarchicalCoherenceAgent(implicit p: Parameters) extends Cohere
trait HasTrackerConflictIO extends Bundle {
val has_acquire_conflict = Bool(OUTPUT)
val has_acquire_match = Bool(OUTPUT)
val has_release_match = Bool(OUTPUT)
}
class ManagerXactTrackerIO(implicit p: Parameters) extends ManagerTLIO()(p)
@ -154,4 +153,17 @@ abstract class XactTracker(implicit p: Parameters) extends CoherenceAgentModule(
def dropPendingBitAtDest(in: DecoupledIO[ProbeToDst]): UInt =
~Fill(in.bits.tlNCachingClients, in.fire()) | ~UIntToOH(in.bits.client_id)
def pinAllReadyValidLow[T <: Data](b: Bundle) {
b.elements.foreach {
_._2 match {
case d: DecoupledIO[_] =>
if(d.ready.dir == OUTPUT) d.ready := Bool(false)
else if(d.valid.dir == OUTPUT) d.valid := Bool(false)
case v: ValidIO[_] => if(v.valid.dir == OUTPUT) v.valid := Bool(false)
case b: Bundle => pinAllReadyValidLow(b)
case _ =>
}
}
}
}