From 0f75ebee92b9cf473ba9f32acae4a2192305b43c Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 15:31:29 -0700
Subject: [PATCH 01/21] async_reg: Rename the file to match scalastyle

---
 src/main/scala/util/{BlackBoxRegs.scala => AsyncResetReg.scala} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename src/main/scala/util/{BlackBoxRegs.scala => AsyncResetReg.scala} (100%)

diff --git a/src/main/scala/util/BlackBoxRegs.scala b/src/main/scala/util/AsyncResetReg.scala
similarity index 100%
rename from src/main/scala/util/BlackBoxRegs.scala
rename to src/main/scala/util/AsyncResetReg.scala

From 7f683eeb24f35dcae473c6887d152cf972135cb5 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 15:33:53 -0700
Subject: [PATCH 02/21] async_regs: Make modules have predictable names

---
 src/main/scala/util/AsyncResetReg.scala | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/main/scala/util/AsyncResetReg.scala b/src/main/scala/util/AsyncResetReg.scala
index 532fdcb0..0af3e693 100644
--- a/src/main/scala/util/AsyncResetReg.scala
+++ b/src/main/scala/util/AsyncResetReg.scala
@@ -63,6 +63,9 @@ class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
   }
 
   io.q := q.asUInt
+
+  override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
+
 }
 
 object AsyncResetReg {

From d83a6dc6afdaa41dd29ca35f249785fd0de1ba06 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 16:47:15 -0700
Subject: [PATCH 03/21] syncregs: Add utilities for Synchronizing Shift
 Registers

---
 src/main/scala/util/SynchronizingReg.scala | 130 +++++++++++++++++++++
 1 file changed, 130 insertions(+)
 create mode 100644 src/main/scala/util/SynchronizingReg.scala

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
new file mode 100644
index 00000000..583c72c6
--- /dev/null
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -0,0 +1,130 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.util
+
+import Chisel._
+
+/** These wrap behavioral 
+  *  shift registers  into specific
+  *  modules to allow for 
+  *  backend flows to replace or constrain
+  *  them properly when used for CDC synchronization,
+  *  rather than buffering.
+  *  
+  *  The 3 different types vary in their reset behavior:
+  *  AsyncResetSynchronizerShiftReg -- asynchronously reset to 0
+  *  SynchronizerShiftRegInit -- synchronously reset to 0
+  *  SynchronizerShiftReg -- no reset, pipeline only.
+  *  
+  */
+
+class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Module {
+
+  require(sync > 0, "Sync must be greater than 0.")
+
+  override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
+
+  val io = new Bundle {
+    val d = UInt(INPUT, width = w)
+    val q = UInt(OUTPUT, width = w)
+  }
+
+  val syncv = List.tabulate(sync) { i =>
+    Module (new AsyncResetRegVec(w, 0)).suggestName(s"sync_${i}")
+  }
+
+  syncv.last.io.d := io.d
+  syncv.last.io.en := Bool(true)
+
+  (syncv.init zip syncv.tail).foreach { case (sink, source) =>
+    sink.io.d := source.io.q
+    sink.io.en := Bool(true)
+  }
+  io.q := syncv.head.io.q
+}
+
+object AsyncResetSynchronizerShiftReg {
+
+  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = {
+    val sync_reg = Module(new AsyncResetSynchronizerShiftReg(in.getWidth, sync))
+    name.foreach{ sync_reg.suggestName(_) }
+
+    sync_reg.io.d := in.asUInt
+    (in.chiselCloneType).fromBits(sync_reg.io.q)
+  }
+
+}
+
+class SynchronizerShiftRegInit(w: Int = 1, sync: Int = 3) extends Module {
+
+  require(sync > 0, "Sync must be greater than 0.")
+
+  override def desiredName = s"SynchronizerShiftRegInit_w${w}_d${sync}"
+
+  val io = new Bundle {
+    val d = UInt(INPUT, width = w)
+    val q = UInt(OUTPUT, width = w)
+  }
+
+  val syncv = List.tabulate(sync) { i =>
+    val r = RegInit(UInt(0, width = w))
+    r.suggestName(s"sync_${i}")
+  }
+
+  syncv.last := io.d
+
+  (syncv.init zip syncv.tail).foreach { case (sink, source) =>
+    sink := source
+  }
+
+  io.q := syncv.head
+
+}
+
+object SynchronizerShiftRegInit {
+
+  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = {
+    val sync_reg = Module(new SynchronizerShiftRegInit(in.getWidth, sync))
+    name.foreach{ sync_reg.suggestName(_) }
+
+    sync_reg.io.d := in.asUInt
+    (in.chiselCloneType).fromBits(sync_reg.io.q)
+  }
+}
+
+
+class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Module {
+
+  require(sync > 0, "Sync must be greater than 0.")
+
+  override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
+
+  val io = new Bundle {
+    val d = UInt(INPUT, width = w)
+    val q = UInt(OUTPUT, width = w)
+  }
+
+  val syncv = List.tabulate(sync) { i =>
+    val r = Reg(UInt(width = w))
+    r.suggestName(s"sync_${i}")
+  }
+
+  syncv.last := io.d
+
+  (syncv.init zip syncv.tail).foreach { case (sink, source) =>
+    sink := source
+  }
+  io.q := syncv.head
+
+}
+
+object SynchronizerShiftReg {
+
+  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = {
+    val sync_reg = Module(new SynchronizerShiftReg(in.getWidth, sync))
+    name.foreach{ sync_reg.suggestName(_) }
+
+    sync_reg.io.d := in.asUInt
+    (in.chiselCloneType).fromBits(sync_reg.io.q)
+  }
+}

From c78ee9f0e4d67aa65d29e8f37c86885dbd66813b Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 17:18:04 -0700
Subject: [PATCH 04/21] syncreg: Refactor common code

---
 src/main/scala/util/SynchronizingReg.scala | 71 +++++++++-------------
 1 file changed, 28 insertions(+), 43 deletions(-)

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index 583c72c6..a77e9b17 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -18,17 +18,30 @@ import Chisel._
   *  
   */
 
-class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Module {
-
+abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module {
   require(sync > 0, "Sync must be greater than 0.")
 
-  override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
-
   val io = new Bundle {
     val d = UInt(INPUT, width = w)
     val q = UInt(OUTPUT, width = w)
   }
 
+}
+
+object AbstractSynchronizerReg {
+
+  def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
+    val sync_reg = Module(gen(in.getWidth, sync))
+    name.foreach{ sync_reg.suggestName(_) }
+    sync_reg.io.d := in.asUInt
+      (in.chiselCloneType).fromBits(sync_reg.io.q)
+  }
+}
+
+class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
+
+  override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
+
   val syncv = List.tabulate(sync) { i =>
     Module (new AsyncResetRegVec(w, 0)).suggestName(s"sync_${i}")
   }
@@ -45,27 +58,15 @@ class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Module {
 
 object AsyncResetSynchronizerShiftReg {
 
-  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = {
-    val sync_reg = Module(new AsyncResetSynchronizerShiftReg(in.getWidth, sync))
-    name.foreach{ sync_reg.suggestName(_) }
-
-    sync_reg.io.d := in.asUInt
-    (in.chiselCloneType).fromBits(sync_reg.io.q)
-  }
-
+  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
+    AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new AsyncResetSynchronizerShiftReg(w, sync)},
+      in, sync, name)
 }
 
-class SynchronizerShiftRegInit(w: Int = 1, sync: Int = 3) extends Module {
-
-  require(sync > 0, "Sync must be greater than 0.")
+class SynchronizerShiftRegInit(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
 
   override def desiredName = s"SynchronizerShiftRegInit_w${w}_d${sync}"
 
-  val io = new Bundle {
-    val d = UInt(INPUT, width = w)
-    val q = UInt(OUTPUT, width = w)
-  }
-
   val syncv = List.tabulate(sync) { i =>
     val r = RegInit(UInt(0, width = w))
     r.suggestName(s"sync_${i}")
@@ -83,27 +84,15 @@ class SynchronizerShiftRegInit(w: Int = 1, sync: Int = 3) extends Module {
 
 object SynchronizerShiftRegInit {
 
-  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = {
-    val sync_reg = Module(new SynchronizerShiftRegInit(in.getWidth, sync))
-    name.foreach{ sync_reg.suggestName(_) }
-
-    sync_reg.io.d := in.asUInt
-    (in.chiselCloneType).fromBits(sync_reg.io.q)
-  }
+  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
+    AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftRegInit(w, sync)},
+      in, sync, name)
 }
 
-
-class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Module {
-
-  require(sync > 0, "Sync must be greater than 0.")
+class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
 
   override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
 
-  val io = new Bundle {
-    val d = UInt(INPUT, width = w)
-    val q = UInt(OUTPUT, width = w)
-  }
-
   val syncv = List.tabulate(sync) { i =>
     val r = Reg(UInt(width = w))
     r.suggestName(s"sync_${i}")
@@ -120,11 +109,7 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Module {
 
 object SynchronizerShiftReg {
 
-  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = {
-    val sync_reg = Module(new SynchronizerShiftReg(in.getWidth, sync))
-    name.foreach{ sync_reg.suggestName(_) }
-
-    sync_reg.io.d := in.asUInt
-    (in.chiselCloneType).fromBits(sync_reg.io.q)
-  }
+  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
+    AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftReg(w, sync)},
+      in, sync, name)
 }

From 3461cb47cca7cd525c0408bc327f1726f51f56fa Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 17:26:38 -0700
Subject: [PATCH 05/21] syncregs: Make Reset catcher use the synchronizer
 primitive

---
 src/main/scala/util/ResetCatchAndSync.scala | 7 +------
 src/main/scala/util/SynchronizingReg.scala  | 2 +-
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala
index f3f68a95..776d94d4 100644
--- a/src/main/scala/util/ResetCatchAndSync.scala
+++ b/src/main/scala/util/ResetCatchAndSync.scala
@@ -15,12 +15,7 @@ class ResetCatchAndSync (sync: Int = 3) extends Module {
     val sync_reset = Bool(OUTPUT)
   }
 
-  val reset_n_catch_reg = Module (new AsyncResetRegVec(sync, 0))
-
-  reset_n_catch_reg.io.en := Bool(true)
-  reset_n_catch_reg.io.d  := Cat(Bool(true), reset_n_catch_reg.io.q >> 1)
-
-  io.sync_reset := ~reset_n_catch_reg.io.q(0)
+  io.sync_reset := ~AsyncResetSynchronizerShiftReg(Bool(true), sync)
 
 }
 
diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index a77e9b17..08069c71 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -31,7 +31,7 @@ abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module
 object AbstractSynchronizerReg {
 
   def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
-    val sync_reg = Module(gen(in.getWidth, sync))
+    val sync_chain = Module(gen(in.getWidth, sync))
     name.foreach{ sync_reg.suggestName(_) }
     sync_reg.io.d := in.asUInt
       (in.chiselCloneType).fromBits(sync_reg.io.q)

From 8b462d15957dcc7b1167d06922d2172d35285cac Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 17:34:07 -0700
Subject: [PATCH 06/21] syncregs: Use common primitives for AsyncQueue grey
 code synchronizers

---
 src/main/scala/util/AsyncQueue.scala       | 21 +++------------------
 src/main/scala/util/SynchronizingReg.scala |  7 ++++---
 2 files changed, 7 insertions(+), 21 deletions(-)

diff --git a/src/main/scala/util/AsyncQueue.scala b/src/main/scala/util/AsyncQueue.scala
index 91e5c05d..e0de910d 100644
--- a/src/main/scala/util/AsyncQueue.scala
+++ b/src/main/scala/util/AsyncQueue.scala
@@ -13,27 +13,12 @@ object GrayCounter {
   }
 }
 
-object UIntSyncChain {
-  def apply(in: UInt, sync: Int, name: String = "gray"): UInt = {
-    val syncv = List.tabulate(sync) { i =>
-      Module (new AsyncResetRegVec(w = in.getWidth, 0)).suggestName(s"${name}_sync_${i}")
-    }
-    syncv.last.io.d := in
-    syncv.last.io.en := Bool(true)
-      (syncv.init zip syncv.tail).foreach { case (sink, source) =>
-        sink.io.d := source.io.q
-        sink.io.en := Bool(true)
-      }
-    syncv.head.io.q
-  }
-}
-
 class AsyncValidSync(sync: Int, desc: String) extends Module {
   val io = new Bundle {
     val in = Bool(INPUT)
     val out = Bool(OUTPUT)
   }
-  io.out := UIntSyncChain(io.in.asUInt, sync, desc)(0)
+  io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
 }
 
 class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, safe: Boolean = true, narrowData: Boolean = false) extends Module {
@@ -55,7 +40,7 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, safe: Boolean =
   val sink_ready = Wire(init = Bool(true))
   val mem = Reg(Vec(depth, gen)) // This does NOT need to be reset at all.
   val widx = GrayCounter(bits+1, io.enq.fire(), !sink_ready, "widx_bin")
-  val ridx = UIntSyncChain(io.ridx, sync, "ridx_gray")
+  val ridx = AsyncResetSynchronizerShiftReg(io.ridx, sync, Some("ridx_gray"))
   val ready = sink_ready && widx =/= (ridx ^ UInt(depth | depth >> 1))
 
   val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
@@ -112,7 +97,7 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int, safe: Boolean = t
 
   val source_ready = Wire(init = Bool(true))
   val ridx = GrayCounter(bits+1, io.deq.fire(), !source_ready, "ridx_bin")
-  val widx = UIntSyncChain(io.widx, sync, "widx_gray")
+  val widx = AsyncResetSynchronizerShiftReg(io.widx, sync, Some("widx_gray"))
   val valid = source_ready && ridx =/= widx
 
   // The mux is safe because timing analysis ensures ridx has reached the register
diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index 08069c71..8660e051 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -32,9 +32,10 @@ object AbstractSynchronizerReg {
 
   def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
     val sync_chain = Module(gen(in.getWidth, sync))
-    name.foreach{ sync_reg.suggestName(_) }
-    sync_reg.io.d := in.asUInt
-      (in.chiselCloneType).fromBits(sync_reg.io.q)
+    name.foreach{ sync_chain.suggestName(_) }
+    sync_chain.io.d := in.asUInt
+
+    (in.chiselCloneType).fromBits(sync_chain.io.q)
   }
 }
 

From 130b24355f67fcbade119814cad7c408932f8cb3 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 17:39:07 -0700
Subject: [PATCH 07/21] syncregs: Use synchronizer primitives for IntXing

---
 src/main/scala/tilelink/IntNodes.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/tilelink/IntNodes.scala b/src/main/scala/tilelink/IntNodes.scala
index aa910f5b..3b9cab83 100644
--- a/src/main/scala/tilelink/IntNodes.scala
+++ b/src/main/scala/tilelink/IntNodes.scala
@@ -6,6 +6,7 @@ import Chisel._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util.SynchronizerShiftReg
 import scala.collection.mutable.ListBuffer
 import scala.math.max
 
@@ -139,7 +140,7 @@ class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
     }
 
     (io.in zip io.out) foreach { case (in, out) =>
-      out := (0 to sync).foldLeft(in) { case (a, _) => RegNext(a) }
+      out := SynchronizerShiftReg(in, sync)
     }
   }
 }

From 4e773f4738606312830735608eb83b406d7c82b3 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 17:42:31 -0700
Subject: [PATCH 08/21] syncregs: Use synchronizer primivites for
 LevelSyncCrossing

---
 src/main/scala/util/Crossing.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/util/Crossing.scala b/src/main/scala/util/Crossing.scala
index 11bc1e28..f6bab310 100644
--- a/src/main/scala/util/Crossing.scala
+++ b/src/main/scala/util/Crossing.scala
@@ -99,7 +99,7 @@ object LevelSyncCrossing {
       val out = Bool(OUTPUT)
     }
 
-    io.out := ShiftRegister(io.in, sync)
+    io.out := SynchronizerShiftReg(io.in, sync)
   }
 
   class SynchronizerFrontend(_clock: Clock) extends Module(Some(_clock)) {

From 85c39b2f97b86be6e0e6c4d5f4fe99cef85edbb3 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 17:47:04 -0700
Subject: [PATCH 09/21] syncregs: Not sure the use case for
 SynchronizerShiftRegInit, so remove it YAGNI

---
 src/main/scala/util/SynchronizingReg.scala | 27 ----------------------
 1 file changed, 27 deletions(-)

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index 8660e051..c803ac82 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -13,7 +13,6 @@ import Chisel._
   *  
   *  The 3 different types vary in their reset behavior:
   *  AsyncResetSynchronizerShiftReg -- asynchronously reset to 0
-  *  SynchronizerShiftRegInit -- synchronously reset to 0
   *  SynchronizerShiftReg -- no reset, pipeline only.
   *  
   */
@@ -64,32 +63,6 @@ object AsyncResetSynchronizerShiftReg {
       in, sync, name)
 }
 
-class SynchronizerShiftRegInit(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
-
-  override def desiredName = s"SynchronizerShiftRegInit_w${w}_d${sync}"
-
-  val syncv = List.tabulate(sync) { i =>
-    val r = RegInit(UInt(0, width = w))
-    r.suggestName(s"sync_${i}")
-  }
-
-  syncv.last := io.d
-
-  (syncv.init zip syncv.tail).foreach { case (sink, source) =>
-    sink := source
-  }
-
-  io.q := syncv.head
-
-}
-
-object SynchronizerShiftRegInit {
-
-  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftRegInit(w, sync)},
-      in, sync, name)
-}
-
 class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
 
   override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"

From 451334ac73340d27d60182544ec87ea6821ca9bd Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 28 Aug 2017 17:18:54 -0700
Subject: [PATCH 10/21] Add 1-deep synchronizer register for output of
 AsyncQueue

---
 src/main/scala/util/AsyncQueue.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/util/AsyncQueue.scala b/src/main/scala/util/AsyncQueue.scala
index e0de910d..7abdfb6c 100644
--- a/src/main/scala/util/AsyncQueue.scala
+++ b/src/main/scala/util/AsyncQueue.scala
@@ -110,7 +110,8 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int, safe: Boolean = t
   // be considered unless the asynchronously reset deq valid register is set.
   // It is possible that bits latches when the source domain is reset / has power cut
   // This is safe, because isolation gates brought mem low before the zeroed widx reached us
-  io.deq.bits  := RegEnable(io.mem(if(narrowData) UInt(0) else index), valid)
+  val deq_bits_nxt = Mux(valid, io.mem(if(narrowData) UInt(0) else index), io.deq.bits)
+  io.deq.bits  := SynchronizerShiftReg(deq_bits_nxt, sync = 1, name = Some("deq_bits_reg"))
 
   val valid_reg = AsyncResetReg(valid.asUInt, "valid_reg")(0)
   io.deq.valid := valid_reg && source_ready

From 483e63da19f061e7ecbce51324f8df315295c1ec Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 11:50:25 -0700
Subject: [PATCH 11/21] synchronizers: Correctly pass the width through

---
 src/main/scala/util/SynchronizingReg.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index c803ac82..e81157d5 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -38,7 +38,7 @@ object AbstractSynchronizerReg {
   }
 }
 
-class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
+class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w, sync) {
 
   override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
 
@@ -63,7 +63,7 @@ object AsyncResetSynchronizerShiftReg {
       in, sync, name)
 }
 
-class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
+class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w, sync) {
 
   override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
 

From bd32f0c12218a12608df5f52325e92c7206feeb6 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 11:58:25 -0700
Subject: [PATCH 12/21] synchronizers: properly pass parameters up to the
 superclass

---
 src/main/scala/util/AsyncResetReg.scala | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/main/scala/util/AsyncResetReg.scala b/src/main/scala/util/AsyncResetReg.scala
index 0af3e693..d6133cdd 100644
--- a/src/main/scala/util/AsyncResetReg.scala
+++ b/src/main/scala/util/AsyncResetReg.scala
@@ -106,3 +106,14 @@ object AsyncResetReg {
   def apply(updateData: UInt): UInt = apply(updateData, resetData=BigInt(0), enable=Bool(true))
   def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData=BigInt(0), enable=Bool(true), Some(name))
 }
+
+
+// While this extends from the SynchronizingShiftRegister
+// classes, it is just a convenience.
+
+class AsyncResetShiftReg
+object AsyncResetShiftRegister(w: Int = 1, depth: Int = 3) extends AbstractSynchronizerReg(w, depth) {
+  override def desiredName = s"AsyncResetShiftReg_w${w}_d{$sync}"
+}
+
+}

From 9dd6c4c32d9166c33ac17f0c5c2b2ec07cb061fb Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 12:00:14 -0700
Subject: [PATCH 13/21] synchronizers: New chisel ways of cloning type and use
 simpler lambda function

---
 src/main/scala/util/AsyncResetReg.scala    | 10 ----------
 src/main/scala/util/SynchronizingReg.scala | 10 +++++-----
 2 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/src/main/scala/util/AsyncResetReg.scala b/src/main/scala/util/AsyncResetReg.scala
index d6133cdd..22419832 100644
--- a/src/main/scala/util/AsyncResetReg.scala
+++ b/src/main/scala/util/AsyncResetReg.scala
@@ -107,13 +107,3 @@ object AsyncResetReg {
   def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData=BigInt(0), enable=Bool(true), Some(name))
 }
 
-
-// While this extends from the SynchronizingShiftRegister
-// classes, it is just a convenience.
-
-class AsyncResetShiftReg
-object AsyncResetShiftRegister(w: Int = 1, depth: Int = 3) extends AbstractSynchronizerReg(w, depth) {
-  override def desiredName = s"AsyncResetShiftReg_w${w}_d{$sync}"
-}
-
-}
diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index e81157d5..edfd112e 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -29,12 +29,12 @@ abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module
 
 object AbstractSynchronizerReg {
 
-  def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
-    val sync_chain = Module(gen(in.getWidth, sync))
+  def apply [T <: Chisel.Data](gen: => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
+    val sync_chain = Module(gen)
     name.foreach{ sync_chain.suggestName(_) }
     sync_chain.io.d := in.asUInt
 
-    (in.chiselCloneType).fromBits(sync_chain.io.q)
+    sync_chain.io.q.asTypeOf(in)
   }
 }
 
@@ -59,7 +59,7 @@ class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Abstract
 object AsyncResetSynchronizerShiftReg {
 
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new AsyncResetSynchronizerShiftReg(w, sync)},
+    AbstractSynchronizerReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)},
       in, sync, name)
 }
 
@@ -84,6 +84,6 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchroniz
 object SynchronizerShiftReg {
 
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftReg(w, sync)},
+    AbstractSynchronizerReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)},
       in, sync, name)
 }

From 8139014c9efa3717155d0341e69cbc243a229b5e Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 12:33:03 -0700
Subject: [PATCH 14/21] syncrhonizers: Remove unused sync from superclass

---
 src/main/scala/util/SynchronizingReg.scala | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index edfd112e..ed0f7bd2 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -17,8 +17,7 @@ import Chisel._
   *  
   */
 
-abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module {
-  require(sync > 0, "Sync must be greater than 0.")
+abstract class AbstractSynchronizerReg(w: Int = 1) extends Module {
 
   val io = new Bundle {
     val d = UInt(INPUT, width = w)
@@ -29,7 +28,7 @@ abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module
 
 object AbstractSynchronizerReg {
 
-  def apply [T <: Chisel.Data](gen: => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
+  def apply [T <: Chisel.Data](gen: => AbstractSynchronizerReg, in: T, name: Option[String] = None): T = {
     val sync_chain = Module(gen)
     name.foreach{ sync_chain.suggestName(_) }
     sync_chain.io.d := in.asUInt
@@ -38,7 +37,8 @@ object AbstractSynchronizerReg {
   }
 }
 
-class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w, sync) {
+class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w) {
+  require(sync > 0, "Sync must be greater than 0.")
 
   override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
 
@@ -59,11 +59,11 @@ class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Abstract
 object AsyncResetSynchronizerShiftReg {
 
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractSynchronizerReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)},
-      in, sync, name)
+    AbstractSynchronizerReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)}, in, name)
 }
 
-class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w, sync) {
+class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w) {
+  require(sync > 0, "Sync must be greater than 0.")
 
   override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
 
@@ -84,6 +84,5 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchroniz
 object SynchronizerShiftReg {
 
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractSynchronizerReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)},
-      in, sync, name)
+    AbstractSynchronizerReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)}, in, name)
 }

From a3bc5f2e33fe98e9c1558557e4219bc84f85cb6f Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 12:59:16 -0700
Subject: [PATCH 15/21] synchronizers: Add a generic shift register and then
 extend from it, since an asynchronously resettable shift register is also a
 useful primitive

---
 src/main/scala/util/SynchronizingReg.scala | 56 ++++++++++++++--------
 1 file changed, 37 insertions(+), 19 deletions(-)

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index ed0f7bd2..34fc2277 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -12,12 +12,16 @@ import Chisel._
   *  rather than buffering.
   *  
   *  The 3 different types vary in their reset behavior:
+  *  AsyncResetShiftReg -- This is identical to the AsyncResetSynchronizerShiftReg, 
+  *      it is just named differently
+  *      to distinguish its use case. This is a ShiftRegister meant for timing, 
+  *      not for synchronization.
   *  AsyncResetSynchronizerShiftReg -- asynchronously reset to 0
   *  SynchronizerShiftReg -- no reset, pipeline only.
   *  
   */
 
-abstract class AbstractSynchronizerReg(w: Int = 1) extends Module {
+abstract class AbstractPipelineReg(w: Int = 1) extends Module {
 
   val io = new Bundle {
     val d = UInt(INPUT, width = w)
@@ -26,43 +30,57 @@ abstract class AbstractSynchronizerReg(w: Int = 1) extends Module {
 
 }
 
-object AbstractSynchronizerReg {
+object AbstractPipelineReg {
 
-  def apply [T <: Chisel.Data](gen: => AbstractSynchronizerReg, in: T, name: Option[String] = None): T = {
-    val sync_chain = Module(gen)
-    name.foreach{ sync_chain.suggestName(_) }
-    sync_chain.io.d := in.asUInt
+  def apply [T <: Chisel.Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
+    val chain = Module(gen)
+    name.foreach{ chain.suggestName(_) }
+    chain.io.d := in.asUInt
 
-    sync_chain.io.q.asTypeOf(in)
+    chain.io.q.asTypeOf(in)
   }
 }
 
-class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w) {
-  require(sync > 0, "Sync must be greater than 0.")
+class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
+  require(depth > 0, "Depth must be greater than 0.")
 
-  override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
+  override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
 
-  val syncv = List.tabulate(sync) { i =>
-    Module (new AsyncResetRegVec(w, 0)).suggestName(s"sync_${i}")
+  val chain = List.tabulate(depth) { i =>
+    Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
   }
 
-  syncv.last.io.d := io.d
-  syncv.last.io.en := Bool(true)
+  chain.last.io.d := io.d
+  chain.last.io.en := Bool(true)
 
-  (syncv.init zip syncv.tail).foreach { case (sink, source) =>
+  (chain.init zip chain.tail).foreach { case (sink, source) =>
     sink.io.d := source.io.q
     sink.io.en := Bool(true)
   }
-  io.q := syncv.head.io.q
+  io.q := chain.head.io.q
+
+}
+
+object AsyncResetShiftReg {
+
+  def apply [T <: Chisel.Data](in: T, depth: Int = 1, init: Int = 0, name: Option[String] = None ): T =
+    AbstractPipelineReg(gen = {new AsyncResetShiftReg(in.getWidth, depth, init)}, in, name)
+}
+
+//Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does
+// not try to merge instances of this with instances of the superclass.
+class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AsyncResetShiftReg(w, depth = sync, name = "sync") {
+  require(sync > 0, "Sync must be greater than 0.")
+  override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
 }
 
 object AsyncResetSynchronizerShiftReg {
 
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractSynchronizerReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)}, in, name)
+    AbstractPipelineReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)}, in, name)
 }
 
-class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w) {
+class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
   require(sync > 0, "Sync must be greater than 0.")
 
   override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
@@ -84,5 +102,5 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchroniz
 object SynchronizerShiftReg {
 
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractSynchronizerReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)}, in, name)
+    AbstractPipelineReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)}, in, name)
 }

From 5df23c5514c6e5dde96f1009fdf75bfd2ac157be Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 5 Sep 2017 15:16:08 -0700
Subject: [PATCH 16/21] Synchronizers: remove some newlines and unncessary
 gen's

---
 src/main/scala/util/SynchronizingReg.scala | 17 ++++-------------
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index 34fc2277..8febe342 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -22,21 +22,17 @@ import Chisel._
   */
 
 abstract class AbstractPipelineReg(w: Int = 1) extends Module {
-
   val io = new Bundle {
     val d = UInt(INPUT, width = w)
     val q = UInt(OUTPUT, width = w)
   }
-
 }
 
 object AbstractPipelineReg {
-
   def apply [T <: Chisel.Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
     val chain = Module(gen)
     name.foreach{ chain.suggestName(_) }
     chain.io.d := in.asUInt
-
     chain.io.q.asTypeOf(in)
   }
 }
@@ -58,16 +54,14 @@ class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String
     sink.io.en := Bool(true)
   }
   io.q := chain.head.io.q
-
 }
 
 object AsyncResetShiftReg {
-
   def apply [T <: Chisel.Data](in: T, depth: Int = 1, init: Int = 0, name: Option[String] = None ): T =
-    AbstractPipelineReg(gen = {new AsyncResetShiftReg(in.getWidth, depth, init)}, in, name)
+    AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
 }
 
-//Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does
+// Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does
 // not try to merge instances of this with instances of the superclass.
 class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AsyncResetShiftReg(w, depth = sync, name = "sync") {
   require(sync > 0, "Sync must be greater than 0.")
@@ -75,9 +69,8 @@ class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AsyncRes
 }
 
 object AsyncResetSynchronizerShiftReg {
-
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractPipelineReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)}, in, name)
+    AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync), in, name)
 }
 
 class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
@@ -96,11 +89,9 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineRe
     sink := source
   }
   io.q := syncv.head
-
 }
 
 object SynchronizerShiftReg {
-
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractPipelineReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)}, in, name)
+    AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
 }

From e9e46db6009a60c2e558ff5b31e2f4db20ee1363 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 5 Sep 2017 15:54:25 -0700
Subject: [PATCH 17/21] sync reg: Rename the file to reflect the more generic
 shift registers also in the file.

---
 src/main/scala/util/{SynchronizingReg.scala => ShiftReg.scala} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename src/main/scala/util/{SynchronizingReg.scala => ShiftReg.scala} (100%)

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/ShiftReg.scala
similarity index 100%
rename from src/main/scala/util/SynchronizingReg.scala
rename to src/main/scala/util/ShiftReg.scala

From 777f052f95c1d3d1d10728303fbe3b48f5fc3bdc Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 5 Sep 2017 17:32:53 -0700
Subject: [PATCH 18/21] regs: Add named/initial value ShiftRegister primitives
 so they are all in one place

---
 src/main/scala/util/ShiftReg.scala | 59 +++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/util/ShiftReg.scala b/src/main/scala/util/ShiftReg.scala
index 8febe342..5d1dfe9d 100644
--- a/src/main/scala/util/ShiftReg.scala
+++ b/src/main/scala/util/ShiftReg.scala
@@ -4,7 +4,64 @@ package freechips.rocketchip.util
 
 import Chisel._
 
-/** These wrap behavioral 
+
+object ShiftReg {
+  /** Similar to Chisel ShiftRegister, but allows the user to
+    * specify a name and initial value. This is different from 
+    * ShiftRegInit in that it allows the enable signal to be specified. 
+    * Returns the n-cycle delayed version of the input signal.
+    *
+    * @param in input to delay
+    * @param n number of cycles to delay
+    * @param en enable the shift
+    * @param name set the elaborated name of the registers.
+    */
+  def apply[T <: Chisel.Data](in: T,
+    n: Int,
+    en: Chisel.Bool = Chisel.Bool(true),
+    name: Option[String] = None): T = {
+    // The order of tests reflects the expected use cases.
+    if (n != 0) {
+      val r = Chisel.RegEnable(apply(in, n-1, en, name), en)
+      name.foreach { na =>  r.suggestName(s"${na}_pipe_${n-1}") }
+      r
+    } else {
+      in
+    }
+  }
+  
+  /** Returns the n-cycle delayed version of the input signal with reset initialization.
+    *
+    * @param in input to delay
+    * @param n number of cycles to delay
+    * @param init reset value for each register in the shift
+    * @param en enable the shift
+    * @param name set the elaborated name of the registers.
+    */
+  def apply[T <: Chisel.Data](in: T, n: Int, init: T, en: Chisel.Bool, name: Option[String]): T = {
+    // The order of tests reflects the expected use cases.
+    if (n != 0) {
+      val r = Chisel.RegEnable(apply(in, n-1, init, en, name), init, en)
+      if (name.isDefined) r.suggestName(s"${name.get}_pipe_${n-1}")
+      r
+    } else {
+      in
+    }
+  }
+
+  def apply[T <: Chisel.Data](in: T, n: Int, init: T, name: Option[String]): T = {
+    apply(in, n, en = Bool(true), name)
+  }
+}
+// Similar to the Chisel ShiftRegister but allows the user to suggest a
+// name to the registers that get instantiated, and
+// to provide a reset value.
+object ShiftRegInit {
+  def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
+  ShiftReg(in, n, init, en = Bool(true), name)
+}
+
+/** These wrap behavioral
   *  shift registers  into specific
   *  modules to allow for 
   *  backend flows to replace or constrain

From 3c4b472f66ae56985b3e4ba433416820c12429cf Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 6 Sep 2017 10:37:59 -0700
Subject: [PATCH 19/21] shift regs: remove some unnecessary primitives, and add
 some that actually are necessary

---
 src/main/scala/util/ShiftReg.scala | 115 +++++++++++++----------------
 1 file changed, 52 insertions(+), 63 deletions(-)

diff --git a/src/main/scala/util/ShiftReg.scala b/src/main/scala/util/ShiftReg.scala
index 5d1dfe9d..3f9d3e44 100644
--- a/src/main/scala/util/ShiftReg.scala
+++ b/src/main/scala/util/ShiftReg.scala
@@ -4,78 +4,34 @@ package freechips.rocketchip.util
 
 import Chisel._
 
-
-object ShiftReg {
-  /** Similar to Chisel ShiftRegister, but allows the user to
-    * specify a name and initial value. This is different from 
-    * ShiftRegInit in that it allows the enable signal to be specified. 
-    * Returns the n-cycle delayed version of the input signal.
-    *
-    * @param in input to delay
-    * @param n number of cycles to delay
-    * @param en enable the shift
-    * @param name set the elaborated name of the registers.
-    */
-  def apply[T <: Chisel.Data](in: T,
-    n: Int,
-    en: Chisel.Bool = Chisel.Bool(true),
-    name: Option[String] = None): T = {
-    // The order of tests reflects the expected use cases.
-    if (n != 0) {
-      val r = Chisel.RegEnable(apply(in, n-1, en, name), en)
-      name.foreach { na =>  r.suggestName(s"${na}_pipe_${n-1}") }
-      r
-    } else {
-      in
-    }
-  }
-  
-  /** Returns the n-cycle delayed version of the input signal with reset initialization.
-    *
-    * @param in input to delay
-    * @param n number of cycles to delay
-    * @param init reset value for each register in the shift
-    * @param en enable the shift
-    * @param name set the elaborated name of the registers.
-    */
-  def apply[T <: Chisel.Data](in: T, n: Int, init: T, en: Chisel.Bool, name: Option[String]): T = {
-    // The order of tests reflects the expected use cases.
-    if (n != 0) {
-      val r = Chisel.RegEnable(apply(in, n-1, init, en, name), init, en)
-      if (name.isDefined) r.suggestName(s"${name.get}_pipe_${n-1}")
-      r
-    } else {
-      in
-    }
-  }
-
-  def apply[T <: Chisel.Data](in: T, n: Int, init: T, name: Option[String]): T = {
-    apply(in, n, en = Bool(true), name)
-  }
-}
 // Similar to the Chisel ShiftRegister but allows the user to suggest a
 // name to the registers that get instantiated, and
 // to provide a reset value.
 object ShiftRegInit {
   def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
-  ShiftReg(in, n, init, en = Bool(true), name)
+    (0 until n).foldLeft(in) {
+      case (next, i) => {
+        val r = Reg(next, next = next, init = init)
+        name.foreach { na => r.suggestName(s"${na}_${i}") }
+        r
+      }
+    }
 }
 
 /** These wrap behavioral
-  *  shift registers  into specific
-  *  modules to allow for 
+  *  shift registers  into specific modules to allow for
   *  backend flows to replace or constrain
   *  them properly when used for CDC synchronization,
   *  rather than buffering.
   *  
-  *  The 3 different types vary in their reset behavior:
+  *  The different types vary in their reset behavior:
   *  AsyncResetShiftReg -- This is identical to the AsyncResetSynchronizerShiftReg, 
-  *      it is just named differently
-  *      to distinguish its use case. This is a ShiftRegister meant for timing, 
+  *      it is just named differently to distinguish its use case.
+  *      This is an async ShiftRegister meant for timing,
   *      not for synchronization.
-  *  AsyncResetSynchronizerShiftReg -- asynchronously reset to 0
-  *  SynchronizerShiftReg -- no reset, pipeline only.
-  *  
+  *  AsyncResetSynchronizerShiftReg -- asynchronously reset to specific value.
+  *  SyncResetSynchronizerShiftReg  -- reset to specific value.
+  *  SynchronizerShiftReg           -- no reset, pipeline only.
   */
 
 abstract class AbstractPipelineReg(w: Int = 1) extends Module {
@@ -114,20 +70,38 @@ class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String
 }
 
 object AsyncResetShiftReg {
-  def apply [T <: Chisel.Data](in: T, depth: Int = 1, init: Int = 0, name: Option[String] = None ): T =
+  def apply [T <: Chisel.Data](in: T, depth: Int, init: Int  = 0, name: Option[String] = None): T =
     AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
+
+  def apply [T <: Chisel.Data](in: T, depth: Int, name: Option[String]): T =
+    apply(in, depth, 0, name)
+
+  def apply [T <: Chisel.Data](in: T, depth: Int, init: T, name: Option[String]): T =
+    apply(in, depth, init.litValue.toInt, name)
+
+  def apply [T <: Chisel.Data](in: T, depth: Int, init: T): T =
+    apply (in, depth, init.litValue.toInt, None)
 }
 
 // Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does
 // not try to merge instances of this with instances of the superclass.
-class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AsyncResetShiftReg(w, depth = sync, name = "sync") {
+class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3, init: Int = 0) extends AsyncResetShiftReg(w, depth = sync, init, name = "sync") {
   require(sync > 0, "Sync must be greater than 0.")
-  override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
+  override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
 }
 
 object AsyncResetSynchronizerShiftReg {
-  def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
-    AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync), in, name)
+  def apply [T <: Chisel.Data](in: T, depth: Int, init: Int  = 0, name: Option[String] = None): T =
+    AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, depth, init), in, name)
+
+  def apply [T <: Chisel.Data](in: T, depth: Int, name: Option[String]): T =
+    apply(in, depth, 0, name)
+
+  def apply [T <: Chisel.Data](in: T, depth: Int, init: T, name: Option[String]): T =
+    apply(in, depth, init.litValue.toInt, name)
+
+  def apply [T <: Chisel.Data](in: T, depth: Int, init: T): T =
+    apply (in, depth, init.litValue.toInt, None)
 }
 
 class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
@@ -148,7 +122,22 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineRe
   io.q := syncv.head
 }
 
+
 object SynchronizerShiftReg {
   def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
     AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
 }
+
+class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3, init: Int = 0) extends AbstractPipelineReg(w) {
+  require (sync >= 0, "Sync must be greater than or equal to 0")
+
+  override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
+
+  io.q := ShiftRegInit(io.d, n = sync, init = init.U, name = Some("sync"))
+
+}
+
+object SyncResetSynchronizerShiftReg {
+  def apply [T <: Chisel.Data](in: T, sync: Int = 3, init: T, name: Option[String] = None): T =
+    AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init.litValue.toInt), in, name)
+}

From 1da6cb85aba287f0bce48dfcb38cc18ded1f5cc7 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 7 Sep 2017 09:51:46 -0700
Subject: [PATCH 20/21] shiftReg: Make it so that register '0' is always
 closest to the q output, regardless of the type of shift register created.

---
 src/main/scala/util/ShiftReg.scala | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/util/ShiftReg.scala b/src/main/scala/util/ShiftReg.scala
index 3f9d3e44..204d8195 100644
--- a/src/main/scala/util/ShiftReg.scala
+++ b/src/main/scala/util/ShiftReg.scala
@@ -9,13 +9,14 @@ import Chisel._
 // to provide a reset value.
 object ShiftRegInit {
   def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
-    (0 until n).foldLeft(in) {
-      case (next, i) => {
-        val r = Reg(next, next = next, init = init)
-        name.foreach { na => r.suggestName(s"${na}_${i}") }
-        r
-      }
+
+  (0 until n).foldRight(in) {
+    case (next, i) => {
+      val r = Reg(next, next = next, init = init)
+      name.foreach { na => r.suggestName(s"${na}_${i}") }
+      r
     }
+  }
 }
 
 /** These wrap behavioral
@@ -51,7 +52,7 @@ object AbstractPipelineReg {
 }
 
 class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
-  require(depth > 0, "Depth must be greater than 0.")
+  require(depth >= 0, "Depth must be greater than or equal to 0.")
 
   override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
 

From 126d56b254a5971ea49153269187293d5f168b5c Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 7 Sep 2017 10:46:55 -0700
Subject: [PATCH 21/21] synchronizers: I learn how foldRight works

---
 src/main/scala/util/ShiftReg.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/util/ShiftReg.scala b/src/main/scala/util/ShiftReg.scala
index 204d8195..917447f8 100644
--- a/src/main/scala/util/ShiftReg.scala
+++ b/src/main/scala/util/ShiftReg.scala
@@ -11,7 +11,7 @@ object ShiftRegInit {
   def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
 
   (0 until n).foldRight(in) {
-    case (next, i) => {
+    case (i, next) => {
       val r = Reg(next, next = next, init = init)
       name.foreach { na => r.suggestName(s"${na}_${i}") }
       r
@@ -52,7 +52,7 @@ object AbstractPipelineReg {
 }
 
 class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
-  require(depth >= 0, "Depth must be greater than or equal to 0.")
+  require(depth > 0, "Depth must be greater than 0.")
 
   override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"