riscv/rocket-chip
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initial vu integration

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This commit is contained in:
Yunsup Lee 2012-02-08 21:43:45 -08:00
parent 10b5a0006c
commit 9285a52f25
4 changed files with 209 additions and 117 deletions
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20
rocket/src/main/scala/consts.scala
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@ -206,6 +206,26 @@ object Constants
val FPU_N = UFix(0, 1); val FPU_N = UFix(0, 1);
val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N; val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N;
val VEC_N = UFix(0, 1);
val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N;
val VEC_X = UFix(0, 1)
val VEC_VL = UFix(0, 1)
val VEC_CFG = UFix(1, 1)
val VCMD_I = UFix(0, 3)
val VCMD_F = UFix(1, 3)
val VCMD_TX = UFix(2, 3)
val VCMD_TF = UFix(3, 3)
val VCMD_MX = UFix(4, 3)
val VCMD_MF = UFix(5, 3)
val VCMD_X = UFix(0, 3)
val VIMM_VLEN = UFix(0, 2)
val VIMM_ALU = UFix(1, 2)
val VIMM_RS1 = UFix(2, 2)
val VIMM_X = UFix(0, 2)
} }
} }

15
rocket/src/main/scala/cpu.scala
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@ -1,8 +1,9 @@
package Top { package Top
import Chisel._; import Chisel._;
import Node._; import Node._;
import Constants._; import Constants._;
import hwacha._
class ioDebug(view: List[String] = null) extends Bundle(view) class ioDebug(view: List[String] = null) extends Bundle(view)
{ {
@ -120,6 +121,16 @@ class rocketProc extends Component
fpu.io.dmem.resp_data := arb.io.cpu.resp_data; fpu.io.dmem.resp_data := arb.io.cpu.resp_data;
dpath.io.fpu <> fpu.io.dpath dpath.io.fpu <> fpu.io.dpath
} }
}
if (HAVE_VEC)
{
val vu = new vu()
vu.io.vec_cmdq <> ctrl.io.vcmdq
vu.io.vec_cmdq <> dpath.io.vcmdq
vu.io.vec_ximm1q <> ctrl.io.vximm1q
vu.io.vec_ximm1q <> dpath.io.vximm1q
vu.io.vec_ximm2q <> ctrl.io.vximm2q
vu.io.vec_ximm2q <> dpath.io.vximm2q
}
} }

82
rocket/src/main/scala/ctrl.scala
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@ -5,6 +5,7 @@ import Node._;
import Constants._ import Constants._
import Instructions._ import Instructions._
import hwacha._
class ioCtrlDpath extends Bundle() class ioCtrlDpath extends Bundle()
{ {
@ -77,6 +78,9 @@ class ioCtrlAll extends Bundle()
val console = new ioConsole(List("rdy")); val console = new ioConsole(List("rdy"));
val imem = new ioImem(List("req_val", "resp_val")).flip(); val imem = new ioImem(List("req_val", "resp_val")).flip();
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack")).flip(); val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack")).flip();
val vcmdq = new io_vec_cmdq(List("ready", "valid"))
val vximm1q = new io_vec_ximm1q(List("ready", "valid"))
val vximm2q = new io_vec_ximm2q(List("ready", "valid"))
val dtlb_val = Bool(OUTPUT); val dtlb_val = Bool(OUTPUT);
val dtlb_kill = Bool(OUTPUT); val dtlb_kill = Bool(OUTPUT);
val dtlb_rdy = Bool(INPUT); val dtlb_rdy = Bool(INPUT);
@ -99,8 +103,12 @@ class rocketCtrl extends Component
val xpr64 = Y; val xpr64 = Y;
val cs = val cs =
ListLookup(io.dpath.inst, ListLookup(io.dpath.inst,
List( N, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N), // eret
Array( // | syscall
// mem_val mul_val div_val renpcr | | privileged
// val brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | |
List(N, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),Array(
BNE-> List(Y, BR_NE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N), BNE-> List(Y, BR_NE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
BEQ-> List(Y, BR_EQ, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N), BEQ-> List(Y, BR_EQ, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
BLT-> List(Y, BR_LT, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N), BLT-> List(Y, BR_LT, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
@ -211,20 +219,68 @@ class rocketCtrl extends Component
FLD-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N), FLD-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSW-> List(Y, BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N), FSW-> List(Y, BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSD-> List(Y, BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N) FSD-> List(Y, BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N)
/* ))
// floating point
FLW-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_FRD, MT_WU,N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N), val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
FLD-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_FRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N), val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0
FSW-> List(FPU_Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_FWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N), val id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
FSD-> List(FPU_Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_FWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
*/ val veccs =
)); ListLookup(io.dpath.inst,
// appvlmask
// | vcmdq
// | | vximm1q
// | | | vximm2q
// val ren2 ren1 vcmd vimm fn | | | | vackq
// | | | | | | | | | | |
List(N,REN_N,REN_N,VCMD_X, VIMM_X, VEC_X ,N,N,N,N,N),Array(
VVCFGIVL-> List(Y,REN_N,REN_Y,VCMD_I, VIMM_VLEN,VEC_CFG,N,Y,Y,N,N),
VSETVL-> List(Y,REN_N,REN_Y,VCMD_I, VIMM_VLEN,VEC_VL ,N,Y,Y,N,N),
VF-> List(Y,REN_Y,REN_Y,VCMD_I, VIMM_ALU, VEC_X ,Y,Y,Y,N,N),
VMVV-> List(Y,REN_N,REN_N,VCMD_TX,VIMM_X, VEC_X ,Y,Y,N,N,N),
VMSV-> List(Y,REN_N,REN_Y,VCMD_TX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VFMVV-> List(Y,REN_N,REN_N,VCMD_TF,VIMM_X, VEC_X ,Y,Y,N,N,N),
FENCE_L_V-> List(Y,REN_N,REN_N,VCMD_F, VIMM_X, VEC_X ,N,Y,N,N,N),
FENCE_G_V-> List(Y,REN_N,REN_N,VCMD_F, VIMM_X, VEC_X ,N,Y,N,N,N),
FENCE_L_CV->List(Y,REN_N,REN_N,VCMD_F, VIMM_X, VEC_X ,N,Y,N,N,Y),
FENCE_G_CV->List(Y,REN_N,REN_N,VCMD_F, VIMM_X, VEC_X ,N,Y,N,N,Y),
VLD-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VLW-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VLWU-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VLH-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VLHU-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VLB-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VLBU-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VSD-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VSW-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VSH-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VSB-> List(Y,REN_N,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VFLD-> List(Y,REN_N,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VFLW-> List(Y,REN_N,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VFSD-> List(Y,REN_N,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VFSW-> List(Y,REN_N,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,N,N),
VLSTD-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VLSTW-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VLSTWU-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VLSTH-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VLSTHU-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VLSTB-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VLSTBU-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VSSTD-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VSSTW-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VSSTH-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VSSTB-> List(Y,REN_Y,REN_Y,VCMD_MX,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VFLSTD-> List(Y,REN_Y,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VFLSTW-> List(Y,REN_Y,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VFSSTD-> List(Y,REN_Y,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N),
VFSSTW-> List(Y,REN_Y,REN_Y,VCMD_MF,VIMM_RS1, VEC_X ,Y,Y,Y,Y,N)
))
val id_vec_val :: id_renv2 :: id_renv1 :: id_sel_vcmd :: id_sel_vimm :: id_fn_vec :: id_vec_appvlmask :: veccs0 = veccs
val id_vec_cmdq_val :: id_vec_ximm1q_val :: id_vec_ximm2q_val :: id_vec_ackq_wait :: Nil = veccs0
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false)); val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false));
val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: csremainder = cs;
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = csremainder;
val id_raddr3 = io.dpath.inst(16,12); val id_raddr3 = io.dpath.inst(16,12);
val id_raddr2 = io.dpath.inst(21,17); val id_raddr2 = io.dpath.inst(21,17);
val id_raddr1 = io.dpath.inst(26,22); val id_raddr1 = io.dpath.inst(26,22);

5
rocket/src/main/scala/dpath.scala
View File

@ -2,8 +2,10 @@ package Top {
import Chisel._ import Chisel._
import Node._; import Node._;
import Constants._ import Constants._
import Instructions._ import Instructions._
import hwacha._
class ioDpathDmem extends Bundle() class ioDpathDmem extends Bundle()
{ {
@ -32,6 +34,9 @@ class ioDpathAll extends Bundle()
val debug = new ioDebug(); val debug = new ioDebug();
val dmem = new ioDpathDmem(); val dmem = new ioDpathDmem();
val imem = new ioDpathImem(); val imem = new ioDpathImem();
val vcmdq = new io_vec_cmdq(List("bits"))
val vximm1q = new io_vec_ximm1q(List("bits"))
val vximm2q = new io_vec_ximm2q(List("bits"))
val ptbr_wen = Bool(OUTPUT); val ptbr_wen = Bool(OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT); val ptbr = UFix(PADDR_BITS, OUTPUT);
val fpu = new ioDpathFPU(); val fpu = new ioDpathFPU();