riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Allow the number of memory channels to be picked at runtime

Browse Source 
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
This commit is contained in:
Palmer Dabbelt
2016-02-17 15:23:30 -08:00
parent 95b065153d
commit 926efd0cab
6 changed files with 78 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
csrc/htif_emulator.h
View File

@ -7,12 +7,20 @@
class htif_emulator_t : public htif_pthread_t
{
int memory_channel_mux_select;
public:
htif_emulator_t(uint32_t memsz_mb, const std::vector<std::string>& args)
: htif_pthread_t(args)
: htif_pthread_t(args),
memory_channel_mux_select(0)
{
this->_memsz_mb = memsz_mb;
}
for (const auto& arg: args) {
if (!strncmp(arg.c_str(), "+memory_channel_mux_select=", 27))
memory_channel_mux_select = atoi(arg.c_str()+27);
}
}
void set_clock_divisor(int divisor, int hold_cycles)
{
@ -22,6 +30,7 @@ class htif_emulator_t : public htif_pthread_t
void start()
{
set_clock_divisor(5, 2);
write_cr(-1, UNCORE_SCR__MEMORY_CHANNEL_MUX_SELECT, memory_channel_mux_select);
htif_pthread_t::start();
}