riscv/rocket-chip
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Update to new privileged ISA... phew

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This commit is contained in:
Andrew Waterman 2013-11-25 04:35:15 -08:00
parent 65b8340cea
commit 924261e2b2
8 changed files with 534 additions and 484 deletions
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1
rocket/src/main/scala/consts.scala
View File

@ -32,6 +32,7 @@ trait ScalarOpConstants {
val IMM_U = UInt(2, 3); val IMM_U = UInt(2, 3);
val IMM_UJ = UInt(3, 3); val IMM_UJ = UInt(3, 3);
val IMM_I = UInt(4, 3); val IMM_I = UInt(4, 3);
val IMM_Z = UInt(5, 3);
val A2_X = Bits("b??", 2) val A2_X = Bits("b??", 2)
val A2_RS2 = UInt(0, 2) val A2_RS2 = UInt(0, 2)

513
rocket/src/main/scala/ctrl.scala
View File

@ -22,9 +22,8 @@ class CtrlDpathIO extends Bundle()
val div_mul_kill = Bool(OUTPUT) val div_mul_kill = Bool(OUTPUT)
val div_val = Bool(OUTPUT); val div_val = Bool(OUTPUT);
val div_kill = Bool(OUTPUT) val div_kill = Bool(OUTPUT)
val sel_wb = UInt(OUTPUT, 2) val csr = UInt(OUTPUT, 3)
val pcr = UInt(OUTPUT, 3) val sret = Bool(OUTPUT)
val eret = Bool(OUTPUT);
val mem_load = Bool(OUTPUT); val mem_load = Bool(OUTPUT);
val wb_load = Bool(OUTPUT) val wb_load = Bool(OUTPUT)
val ex_fp_val= Bool(OUTPUT); val ex_fp_val= Bool(OUTPUT);
@ -34,7 +33,6 @@ class CtrlDpathIO extends Bundle()
val ex_predicted_taken = Bool(OUTPUT) val ex_predicted_taken = Bool(OUTPUT)
val mem_wen = Bool(OUTPUT); val mem_wen = Bool(OUTPUT);
val wb_wen = Bool(OUTPUT); val wb_wen = Bool(OUTPUT);
val wb_valid = Bool(OUTPUT)
val ex_mem_type = Bits(OUTPUT, 3) val ex_mem_type = Bits(OUTPUT, 3)
val ex_rs2_val = Bool(OUTPUT) val ex_rs2_val = Bool(OUTPUT)
val ex_rocc_val = Bool(OUTPUT) val ex_rocc_val = Bool(OUTPUT)
@ -42,6 +40,7 @@ class CtrlDpathIO extends Bundle()
val mem_ll_bypass_rs1 = Bool(OUTPUT) val mem_ll_bypass_rs1 = Bool(OUTPUT)
val mem_ll_bypass_rs2 = Bool(OUTPUT) val mem_ll_bypass_rs2 = Bool(OUTPUT)
// exception handling // exception handling
val retire = Bool(OUTPUT)
val exception = Bool(OUTPUT); val exception = Bool(OUTPUT);
val cause = UInt(OUTPUT, 6); val cause = UInt(OUTPUT, 6);
val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault
@ -59,7 +58,7 @@ class CtrlDpathIO extends Bundle()
val status = new Status().asInput val status = new Status().asInput
val fp_sboard_clr = Bool(INPUT); val fp_sboard_clr = Bool(INPUT);
val fp_sboard_clra = UInt(INPUT, 5); val fp_sboard_clra = UInt(INPUT, 5);
val pcr_replay = Bool(INPUT) val csr_replay = Bool(INPUT)
} }
abstract trait DecodeConstants abstract trait DecodeConstants
@ -67,15 +66,15 @@ abstract trait DecodeConstants
val xpr64 = Y; val xpr64 = Y;
val decode_default = val decode_default =
// fence.i // fence.i
// jalr mul_val | eret // jalr mul_val | sret
// fp_val | renx2 | div_val | | syscall // fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged // | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next // val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
List(N, X,X,BR_X, X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,WB_X, PCR.X,N,X,X,X,X,X,X) List(N, X,X,BR_X, X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,CSR.X,N,X,X,X,X,X)
val table: Array[(UInt, List[UInt])] val table: Array[(UInt, List[UInt])]
} }
@ -83,226 +82,223 @@ abstract trait DecodeConstants
object XDecode extends DecodeConstants object XDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// fence.i // fence.i
// jalr mul_val | eret // jalr mul_val | sret
// fp_val | renx2 | div_val | | syscall // fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged // | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next // val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PCHI,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PCHI,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
LB-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LB-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N),
LH-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LH-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N),
LW-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LW-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,N),
LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,N),
LBU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LBU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,CSR.N,N,N,N,N,N,N),
LHU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LHU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,CSR.N,N,N,N,N,N,N),
LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,CSR.N,N,N,N,N,N,N),
SB-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), SB-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,CSR.N,N,N,N,N,N,N),
SH-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), SH-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,CSR.N,N,N,N,N,N,N),
SW-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), SW-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N),
AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOXOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOXOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOXOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOXOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
LR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), LR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
LR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), LR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
SC_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), SC_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
SC_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), SC_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
LUI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LUI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
XORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), XORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
AND-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), AND-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
OR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), OR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
XOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), XOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,Y,N,N,N,N), SCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,Y,N,N,N),
SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.S,N,N,N,Y,N,N,N), SRET-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,Y,N,N,N,N),
CLEARPCR-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.C,N,N,N,Y,N,N,N), FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,Y,N),
ERET-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,Y,N,Y,N,N,N), FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,Y,N,N,Y,N,N),
FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,Y,N), CSRRW-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N),
FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,Y,N,N,N,Y,N,N), CSRRS-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N),
MFPCR-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.F,N,N,N,Y,N,N,N), CSRRC-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N),
MTPCR-> List(Y, N,N,BR_N, N,Y,N,A2_RS2, A1_ZERO,IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.T,N,N,N,Y,N,N,N), CSRRWI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N),
RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WB_TSC,PCR.N,N,N,N,N,N,N,N), CSRRSI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N),
RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WB_TSC,PCR.N,N,N,N,N,N,N,N), CSRRCI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N))
RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WB_IRT,PCR.N,N,N,N,N,N,N,N))
} }
object FDecode extends DecodeConstants object FDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// fence.i // fence.i
// jalr mul_val | eret // jalr mul_val | sret
// fp_val | renx2 | div_val | | syscall // fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged // | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next // val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
FCVT_S_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMIN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMIN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMIN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMIN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMAX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMAX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMAX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMAX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMUL_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMUL_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMUL_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMUL_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FNMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_W_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_W_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_WU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_WU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_WU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_WU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_L_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_L_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_L_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_L_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_LU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_LU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_LU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_LU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FEQ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FEQ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FEQ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FEQ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FLT_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLT_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FLT_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLT_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FLE_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLE_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FLE_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLE_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FMV_S_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMV_S_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMV_D_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMV_D_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_S_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_S_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_S_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_S_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FRSR-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
FSSR-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,CSR.N,N,N,N,N,N,N),
FLW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), FSW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
FLD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), FSD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N))
FSW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
FSD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N))
} }
object RoCCDecode extends DecodeConstants object RoCCDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// fence.i // fence.i
// jalr mul_val | eret // jalr mul_val | sret
// fp_val | renx2 | div_val | | syscall // fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged // | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next // val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM0_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM0_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM0_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM0_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM0_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM1_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM1_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM1_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM1_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM1_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM2_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM2_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM2_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM2_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM2_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM3_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM3_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM3_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM3_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM3_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N)) CUSTOM3_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N))
} }
class Control(implicit conf: RocketConfiguration) extends Module class Control(implicit conf: RocketConfiguration) extends Module
@ -333,12 +329,12 @@ class Control(implicit conf: RocketConfiguration) extends Module
val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs
val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0 val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0
val (id_mem_val: Bool) :: id_mem_cmd :: id_mem_type :: (id_mul_val: Bool) :: (id_div_val: Bool) :: (id_wen: Bool) :: id_sel_wb :: cs2 = cs1 val (id_mem_val: Bool) :: id_mem_cmd :: id_mem_type :: (id_mul_val: Bool) :: (id_div_val: Bool) :: (id_wen: Bool) :: cs2 = cs1
val id_pcr :: (id_fence_i: Bool) :: (id_eret: Bool) :: (id_syscall: Bool) :: (id_privileged: Bool) :: (id_replay_next: Bool) :: (id_fence: Bool) :: (id_amo: Bool) :: Nil = cs2 val id_csr :: (id_fence_i: Bool) :: (id_sret: Bool) :: (id_syscall: Bool) :: (id_replay_next: Bool) :: (id_fence: Bool) :: (id_amo: Bool) :: Nil = cs2
val ex_reg_xcpt_interrupt = Reg(init=Bool(false)) val ex_reg_xcpt_interrupt = Reg(init=Bool(false))
val ex_reg_valid = Reg(init=Bool(false)) val ex_reg_valid = Reg(init=Bool(false))
val ex_reg_eret = Reg(init=Bool(false)) val ex_reg_sret = Reg(init=Bool(false))
val ex_reg_wen = Reg(init=Bool(false)) val ex_reg_wen = Reg(init=Bool(false))
val ex_reg_fp_wen = Reg(init=Bool(false)) val ex_reg_fp_wen = Reg(init=Bool(false))
val ex_reg_flush_inst = Reg(init=Bool(false)) val ex_reg_flush_inst = Reg(init=Bool(false))
@ -351,7 +347,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val ex_reg_rocc_val = Reg(init=Bool(false)) val ex_reg_rocc_val = Reg(init=Bool(false))
val ex_reg_replay_next = Reg(init=Bool(false)) val ex_reg_replay_next = Reg(init=Bool(false))
val ex_reg_load_use = Reg(init=Bool(false)) val ex_reg_load_use = Reg(init=Bool(false))
val ex_reg_pcr = Reg(init=PCR.N) val ex_reg_csr = Reg(init=CSR.N)
val ex_reg_br_type = Reg(init=BR_N) val ex_reg_br_type = Reg(init=BR_N)
val ex_reg_mem_cmd = Reg(Bits()) val ex_reg_mem_cmd = Reg(Bits())
val ex_reg_mem_type = Reg(Bits()) val ex_reg_mem_type = Reg(Bits())
@ -359,7 +355,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val mem_reg_xcpt_interrupt = Reg(init=Bool(false)) val mem_reg_xcpt_interrupt = Reg(init=Bool(false))
val mem_reg_valid = Reg(init=Bool(false)) val mem_reg_valid = Reg(init=Bool(false))
val mem_reg_eret = Reg(init=Bool(false)) val mem_reg_sret = Reg(init=Bool(false))
val mem_reg_wen = Reg(init=Bool(false)) val mem_reg_wen = Reg(init=Bool(false))
val mem_reg_fp_wen = Reg(init=Bool(false)) val mem_reg_fp_wen = Reg(init=Bool(false))
val mem_reg_flush_inst = Reg(init=Bool(false)) val mem_reg_flush_inst = Reg(init=Bool(false))
@ -370,18 +366,18 @@ class Control(implicit conf: RocketConfiguration) extends Module
val mem_reg_rocc_val = Reg(init=Bool(false)) val mem_reg_rocc_val = Reg(init=Bool(false))
val mem_reg_replay = Reg(init=Bool(false)) val mem_reg_replay = Reg(init=Bool(false))
val mem_reg_replay_next = Reg(init=Bool(false)) val mem_reg_replay_next = Reg(init=Bool(false))
val mem_reg_pcr = Reg(init=PCR.N) val mem_reg_csr = Reg(init=CSR.N)
val mem_reg_cause = Reg(UInt()) val mem_reg_cause = Reg(UInt())
val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_slow_bypass = Reg(Bool())
val wb_reg_valid = Reg(init=Bool(false)) val wb_reg_valid = Reg(init=Bool(false))
val wb_reg_pcr = Reg(init=PCR.N) val wb_reg_csr = Reg(init=CSR.N)
val wb_reg_wen = Reg(init=Bool(false)) val wb_reg_wen = Reg(init=Bool(false))
val wb_reg_fp_wen = Reg(init=Bool(false)) val wb_reg_fp_wen = Reg(init=Bool(false))
val wb_reg_rocc_val = Reg(init=Bool(false)) val wb_reg_rocc_val = Reg(init=Bool(false))
val wb_reg_flush_inst = Reg(init=Bool(false)) val wb_reg_flush_inst = Reg(init=Bool(false))
val wb_reg_mem_val = Reg(init=Bool(false)) val wb_reg_mem_val = Reg(init=Bool(false))
val wb_reg_eret = Reg(init=Bool(false)) val wb_reg_sret = Reg(init=Bool(false))
val wb_reg_xcpt = Reg(init=Bool(false)) val wb_reg_xcpt = Reg(init=Bool(false))
val wb_reg_replay = Reg(init=Bool(false)) val wb_reg_replay = Reg(init=Bool(false))
val wb_reg_cause = Reg(UInt()) val wb_reg_cause = Reg(UInt())
@ -411,9 +407,18 @@ class Control(implicit conf: RocketConfiguration) extends Module
def checkExceptions(x: Seq[(Bool, UInt)]) = def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x)) (x.map(_._1).reduce(_||_), PriorityMux(x))
// flush pipeline on PCR writes that may have side effects val id_csr_addr = io.dpath.inst(31,20)
val id_pcr_flush = id_pcr != PCR.N && id_pcr != PCR.F && val id_csr_en = id_csr != CSR.N
id_raddr1 != PCR.SUP0 && id_raddr1 != PCR.SUP1 && id_raddr1 != PCR.EPC val id_csr_ren = id_raddr1 === UInt(0) && Vec(CSR.S, CSR.C).contains(id_csr)
val id_csr_privileged =
id_csr_addr(9,8) != UInt(0) && id_csr_ren ||
id_csr_addr(11,10) != UInt(0) && id_csr_en
val id_csr_invalid = id_csr_en &&
!Vec(CSRs.all.map(a => UInt(a))).contains(id_csr_addr)
// flush pipeline on CSR writes that may have side effects
val id_csr_flush = id_csr_en && !id_csr_ren &&
id_csr_addr != CSRs.sup0 && id_csr_addr != CSRs.sup1 && id_csr_addr != CSRs.epc
val id_privileged = id_sret || id_csr_privileged
// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE) // stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
val id_amo_aq = io.dpath.inst(26) val id_amo_aq = io.dpath.inst(26)
@ -423,13 +428,13 @@ class Control(implicit conf: RocketConfiguration) extends Module
val id_fence_ok = io.dmem.ordered && !ex_reg_mem_val && val id_fence_ok = io.dmem.ordered && !ex_reg_mem_val &&
(Bool(conf.rocc.isEmpty) || !id_rocc_busy) (Bool(conf.rocc.isEmpty) || !id_rocc_busy)
id_reg_fence := id_fence_next || id_reg_fence && !id_fence_ok id_reg_fence := id_fence_next || id_reg_fence && !id_fence_ok
val id_do_fence = id_amo && id_amo_aq || id_fence_i || id_reg_fence && (id_mem_val || id_rocc_val) || id_pcr_flush val id_do_fence = id_amo && id_amo_aq || id_fence_i || id_reg_fence && (id_mem_val || id_rocc_val) || id_csr_flush
val (id_xcpt, id_cause) = checkExceptions(List( val (id_xcpt, id_cause) = checkExceptions(List(
(id_interrupt, id_interrupt_cause), (id_interrupt, id_interrupt_cause),
(io.imem.resp.bits.xcpt_ma, UInt(0)), (io.imem.resp.bits.xcpt_ma, UInt(0)),
(io.imem.resp.bits.xcpt_if, UInt(1)), (io.imem.resp.bits.xcpt_if, UInt(1)),
(!id_int_val.toBool, UInt(2)), (!id_int_val.toBool || id_csr_invalid, UInt(2)),
(id_privileged && !io.dpath.status.s, UInt(3)), (id_privileged && !io.dpath.status.s, UInt(3)),
(id_fp_val && !io.dpath.status.ef, UInt(4)), (id_fp_val && !io.dpath.status.ef, UInt(4)),
(id_syscall, UInt(6)), (id_syscall, UInt(6)),
@ -446,13 +451,13 @@ class Control(implicit conf: RocketConfiguration) extends Module
ex_reg_valid := Bool(false); ex_reg_valid := Bool(false);
ex_reg_wen := Bool(false); ex_reg_wen := Bool(false);
ex_reg_fp_wen := Bool(false); ex_reg_fp_wen := Bool(false);
ex_reg_eret := Bool(false); ex_reg_sret := Bool(false)
ex_reg_flush_inst := Bool(false); ex_reg_flush_inst := Bool(false);
ex_reg_fp_val := Bool(false) ex_reg_fp_val := Bool(false)
ex_reg_rocc_val := Bool(false) ex_reg_rocc_val := Bool(false)
ex_reg_replay_next := Bool(false) ex_reg_replay_next := Bool(false)
ex_reg_load_use := Bool(false) ex_reg_load_use := Bool(false)
ex_reg_pcr := PCR.N ex_reg_csr := CSR.N
ex_reg_br_type := BR_N ex_reg_br_type := BR_N
ex_reg_xcpt := Bool(false) ex_reg_xcpt := Bool(false)
} }
@ -463,14 +468,14 @@ class Control(implicit conf: RocketConfiguration) extends Module
ex_reg_div_mul_val := id_mul_val || id_div_val ex_reg_div_mul_val := id_mul_val || id_div_val
ex_reg_mem_val := id_mem_val.toBool; ex_reg_mem_val := id_mem_val.toBool;
ex_reg_valid := Bool(true) ex_reg_valid := Bool(true)
ex_reg_pcr := id_pcr ex_reg_csr := id_csr
ex_reg_wen := id_wen && id_waddr != UInt(0) ex_reg_wen := id_wen
ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen
ex_reg_eret := id_eret.toBool; ex_reg_sret := id_sret
ex_reg_flush_inst := id_fence_i ex_reg_flush_inst := id_fence_i
ex_reg_fp_val := id_fp_val ex_reg_fp_val := id_fp_val
ex_reg_rocc_val := id_rocc_val.toBool ex_reg_rocc_val := id_rocc_val.toBool
ex_reg_replay_next := id_replay_next || id_pcr_flush ex_reg_replay_next := id_replay_next || id_csr_flush
ex_reg_load_use := id_load_use ex_reg_load_use := id_load_use
ex_reg_mem_cmd := id_mem_cmd ex_reg_mem_cmd := id_mem_cmd
ex_reg_mem_type := id_mem_type.toUInt ex_reg_mem_type := id_mem_type.toUInt
@ -499,10 +504,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
when (ctrl_killx) { when (ctrl_killx) {
mem_reg_valid := Bool(false); mem_reg_valid := Bool(false);
mem_reg_pcr := PCR.N mem_reg_csr := CSR.N
mem_reg_wen := Bool(false); mem_reg_wen := Bool(false);
mem_reg_fp_wen := Bool(false); mem_reg_fp_wen := Bool(false);
mem_reg_eret := Bool(false); mem_reg_sret := Bool(false)
mem_reg_mem_val := Bool(false); mem_reg_mem_val := Bool(false);
mem_reg_flush_inst := Bool(false); mem_reg_flush_inst := Bool(false);
mem_reg_fp_val := Bool(false) mem_reg_fp_val := Bool(false)
@ -512,10 +517,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
} }
.otherwise { .otherwise {
mem_reg_valid := ex_reg_valid mem_reg_valid := ex_reg_valid
mem_reg_pcr := ex_reg_pcr mem_reg_csr := ex_reg_csr
mem_reg_wen := ex_reg_wen; mem_reg_wen := ex_reg_wen;
mem_reg_fp_wen := ex_reg_fp_wen; mem_reg_fp_wen := ex_reg_fp_wen;
mem_reg_eret := ex_reg_eret; mem_reg_sret := ex_reg_sret
mem_reg_mem_val := ex_reg_mem_val; mem_reg_mem_val := ex_reg_mem_val;
mem_reg_flush_inst := ex_reg_flush_inst; mem_reg_flush_inst := ex_reg_flush_inst;
mem_reg_fp_val := ex_reg_fp_val mem_reg_fp_val := ex_reg_fp_val
@ -533,7 +538,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
(mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11)))) (mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11))))
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_rocc_val || mem_reg_pcr != PCR.N) val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_rocc_val || mem_reg_csr != CSR.N)
val replay_mem = ll_wb_kill_mem || mem_reg_replay || fpu_kill_mem val replay_mem = ll_wb_kill_mem || mem_reg_replay || fpu_kill_mem
val killm_common = ll_wb_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid val killm_common = ll_wb_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem
@ -544,10 +549,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
when (ctrl_killm) { when (ctrl_killm) {
wb_reg_valid := Bool(false) wb_reg_valid := Bool(false)
wb_reg_pcr := PCR.N wb_reg_csr := CSR.N
wb_reg_wen := Bool(false); wb_reg_wen := Bool(false);
wb_reg_fp_wen := Bool(false); wb_reg_fp_wen := Bool(false);
wb_reg_eret := Bool(false); wb_reg_sret := Bool(false)
wb_reg_flush_inst := Bool(false); wb_reg_flush_inst := Bool(false);
wb_reg_mem_val := Bool(false) wb_reg_mem_val := Bool(false)
wb_reg_div_mul_val := Bool(false); wb_reg_div_mul_val := Bool(false);
@ -556,10 +561,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
} }
.otherwise { .otherwise {
wb_reg_valid := mem_reg_valid wb_reg_valid := mem_reg_valid
wb_reg_pcr := mem_reg_pcr wb_reg_csr := mem_reg_csr
wb_reg_wen := mem_reg_wen; wb_reg_wen := mem_reg_wen;
wb_reg_fp_wen := mem_reg_fp_wen; wb_reg_fp_wen := mem_reg_fp_wen;
wb_reg_eret := mem_reg_eret && !mem_reg_replay wb_reg_sret := mem_reg_sret && !mem_reg_replay
wb_reg_flush_inst := mem_reg_flush_inst; wb_reg_flush_inst := mem_reg_flush_inst;
wb_reg_mem_val := mem_reg_mem_val wb_reg_mem_val := mem_reg_mem_val
wb_reg_div_mul_val := mem_reg_div_mul_val wb_reg_div_mul_val := mem_reg_div_mul_val
@ -568,7 +573,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
} }
val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay || val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay ||
io.dpath.pcr_replay || Bool(!conf.rocc.isEmpty) && wb_reg_rocc_val && !io.rocc.cmd.ready io.dpath.csr_replay || Bool(!conf.rocc.isEmpty) && wb_reg_rocc_val && !io.rocc.cmd.ready
class Scoreboard(n: Int) class Scoreboard(n: Int)
{ {
@ -602,24 +607,25 @@ class Control(implicit conf: RocketConfiguration) extends Module
fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra) fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra)
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
id_csr_en && !io.fpu.fcsr_rdy ||
io.fpu.dec.ren1 && fp_sboard.readBypassed(id_raddr1) || io.fpu.dec.ren1 && fp_sboard.readBypassed(id_raddr1) ||
io.fpu.dec.ren2 && fp_sboard.readBypassed(id_raddr2) || io.fpu.dec.ren2 && fp_sboard.readBypassed(id_raddr2) ||
io.fpu.dec.ren3 && fp_sboard.readBypassed(id_raddr3) || io.fpu.dec.ren3 && fp_sboard.readBypassed(id_raddr3) ||
io.fpu.dec.wen && fp_sboard.readBypassed(id_waddr) io.fpu.dec.wen && fp_sboard.readBypassed(id_waddr)
} else Bool(false) } else Bool(false)
// write cause to PCR on an exception // write CAUSE CSR on an exception
io.dpath.exception := wb_reg_xcpt io.dpath.exception := wb_reg_xcpt
io.dpath.cause := wb_reg_cause io.dpath.cause := wb_reg_cause
io.dpath.badvaddr_wen := wb_reg_xcpt && (wb_reg_cause === UInt(10) || wb_reg_cause === UInt(11)) io.dpath.badvaddr_wen := wb_reg_xcpt // don't care for non-memory exceptions
// control transfer from ex/wb // control transfer from ex/wb
take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_eret take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_sret
take_pc := take_pc_ex || take_pc_wb; take_pc := take_pc_ex || take_pc_wb;
io.dpath.sel_pc := io.dpath.sel_pc :=
Mux(wb_reg_xcpt, PC_PCR, // exception Mux(wb_reg_xcpt, PC_PCR, // exception
Mux(wb_reg_eret, PC_PCR, // eret instruction Mux(wb_reg_sret, PC_PCR, // sret instruction
Mux(replay_wb, PC_WB, // replay Mux(replay_wb, PC_WB, // replay
PC_EX)))// branch/jal[r] PC_EX)))// branch/jal[r]
@ -637,7 +643,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr) io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr)
val id_ex_hazard = data_hazard_ex && (ex_reg_pcr != PCR.N || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val || ex_reg_rocc_val) || val id_ex_hazard = data_hazard_ex && (ex_reg_csr != CSR.N || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val || ex_reg_rocc_val) ||
fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val) fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val)
// stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage. // stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage.
@ -653,7 +659,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr) io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr)
val id_mem_hazard = data_hazard_mem && (mem_reg_pcr != PCR.N || mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val || mem_reg_fp_val || mem_reg_rocc_val) || val id_mem_hazard = data_hazard_mem && (mem_reg_csr != CSR.N || mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val || mem_reg_fp_val || mem_reg_rocc_val) ||
fp_data_hazard_mem && mem_reg_fp_val fp_data_hazard_mem && mem_reg_fp_val
id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem) id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
@ -707,10 +713,9 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dpath.ex_wen := ex_reg_wen; io.dpath.ex_wen := ex_reg_wen;
io.dpath.mem_wen := mem_reg_wen; io.dpath.mem_wen := mem_reg_wen;
io.dpath.wb_wen := wb_reg_wen && !replay_wb io.dpath.wb_wen := wb_reg_wen && !replay_wb
io.dpath.wb_valid := wb_reg_valid && !replay_wb io.dpath.retire := wb_reg_valid && !replay_wb
io.dpath.sel_wb := id_sel_wb.toUInt io.dpath.csr := wb_reg_csr
io.dpath.pcr := wb_reg_pcr.toUInt io.dpath.sret := wb_reg_sret
io.dpath.eret := wb_reg_eret
io.dpath.ex_mem_type := ex_reg_mem_type io.dpath.ex_mem_type := ex_reg_mem_type
io.dpath.ex_br_type := ex_reg_br_type ^ ex_reg_btb_hit io.dpath.ex_br_type := ex_reg_br_type ^ ex_reg_btb_hit
io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val

41
rocket/src/main/scala/dpath.scala
View File

@ -26,7 +26,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val ex_reg_sel_alu2 = Reg(UInt()) val ex_reg_sel_alu2 = Reg(UInt())
val ex_reg_sel_alu1 = Reg(UInt()) val ex_reg_sel_alu1 = Reg(UInt())
val ex_reg_sel_imm = Reg(UInt()) val ex_reg_sel_imm = Reg(UInt())
val ex_reg_ctrl_sel_wb = Reg(UInt())
val ex_reg_kill = Reg(Bool()) val ex_reg_kill = Reg(Bool())
val ex_reg_rs1_bypass = Reg(Bool()) val ex_reg_rs1_bypass = Reg(Bool())
val ex_reg_rs1_lsb = Reg(Bits()) val ex_reg_rs1_lsb = Reg(Bits())
@ -50,7 +49,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val wb_reg_ll_wb = Reg(init=Bool(false)) val wb_reg_ll_wb = Reg(init=Bool(false))
val wb_wdata = Bits() val wb_wdata = Bits()
val wb_reg_rs2 = Reg(Bits()) val wb_reg_rs2 = Reg(Bits())
val wb_wen = io.ctrl.wb_wen && io.ctrl.wb_valid || wb_reg_ll_wb val wb_wen = io.ctrl.wb_wen || wb_reg_ll_wb
// instruction decode stage // instruction decode stage
val id_inst = io.imem.resp.bits.data val id_inst = io.imem.resp.bits.data
@ -83,13 +82,16 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val sign = inst(31).toSInt val sign = inst(31).toSInt
val b30_20 = Mux(sel === IMM_U, inst(30,20).toSInt, sign) val b30_20 = Mux(sel === IMM_U, inst(30,20).toSInt, sign)
val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign, inst(19,12).toSInt) val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign, inst(19,12).toSInt)
val b11 = Mux(sel === IMM_U, SInt(0), val b11 = Mux(sel === IMM_U || sel === IMM_Z, SInt(0),
Mux(sel === IMM_UJ, inst(20).toSInt, Mux(sel === IMM_UJ, inst(20).toSInt,
Mux(sel === IMM_SB, inst(7).toSInt, sign))) Mux(sel === IMM_SB, inst(7).toSInt, sign)))
val b10_5 = Mux(sel === IMM_U, Bits(0), inst(30,25)) val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, Bits(0), inst(30,25))
val b4_1 = Mux(sel === IMM_U, Bits(0), val b4_1 = Mux(sel === IMM_U, Bits(0),
Mux(sel === IMM_S || sel === IMM_SB, inst(11,8), inst(24,21))) Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Bits(0))) Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
val b0 = Mux(sel === IMM_S, inst(7),
Mux(sel === IMM_I, inst(20),
Mux(sel === IMM_Z, inst(15), Bits(0))))
Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).toSInt Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).toSInt
} }
@ -107,7 +109,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
ex_reg_sel_alu2 := io.ctrl.sel_alu2 ex_reg_sel_alu2 := io.ctrl.sel_alu2
ex_reg_sel_alu1 := io.ctrl.sel_alu1 ex_reg_sel_alu1 := io.ctrl.sel_alu1
ex_reg_sel_imm := io.ctrl.sel_imm ex_reg_sel_imm := io.ctrl.sel_imm
ex_reg_ctrl_sel_wb := io.ctrl.sel_wb
ex_reg_rs1_bypass := id_rs1_bypass && io.ctrl.ren1 ex_reg_rs1_bypass := id_rs1_bypass && io.ctrl.ren1
ex_reg_rs2_bypass := id_rs2_bypass && io.ctrl.ren2 ex_reg_rs2_bypass := id_rs2_bypass && io.ctrl.ren2
when (io.ctrl.ren1) { when (io.ctrl.ren1) {
@ -198,15 +199,16 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
require(io.dmem.req.bits.tag.getWidth >= 6) require(io.dmem.req.bits.tag.getWidth >= 6)
// processor control regfile read // processor control regfile read
val pcr = Module(new PCR) val pcr = Module(new CSRFile)
pcr.io.host <> io.host pcr.io.host <> io.host
pcr.io <> io.ctrl pcr.io <> io.ctrl
pcr.io <> io.fpu
pcr.io.pc := wb_reg_pc pcr.io.pc := wb_reg_pc
io.ctrl.pcr_replay := pcr.io.replay io.ctrl.csr_replay := pcr.io.replay
io.ptw.ptbr := pcr.io.ptbr io.ptw.ptbr := pcr.io.ptbr
io.ptw.invalidate := pcr.io.fatc io.ptw.invalidate := pcr.io.fatc
io.ptw.eret := io.ctrl.eret io.ptw.sret := io.ctrl.sret
io.ptw.status := pcr.io.status io.ptw.status := pcr.io.status
// branch resolution logic // branch resolution logic
@ -220,21 +222,12 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2, Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2,
io.ctrl.ex_br_type === BR_J)))))) io.ctrl.ex_br_type === BR_J))))))
val tsc_reg = WideCounter(64)
val irt_reg = WideCounter(64, io.ctrl.wb_valid)
// writeback select mux
val ex_wdata =
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg.value,
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg.value,
alu.io.out)).toBits // WB_ALU
// memory stage // memory stage
mem_reg_kill := ex_reg_kill mem_reg_kill := ex_reg_kill
when (!ex_reg_kill) { when (!ex_reg_kill) {
mem_reg_pc := ex_reg_pc mem_reg_pc := ex_reg_pc
mem_reg_inst := ex_reg_inst mem_reg_inst := ex_reg_inst
mem_reg_wdata := ex_wdata mem_reg_wdata := alu.io.out
when (io.ctrl.ex_rs2_val) { when (io.ctrl.ex_rs2_val) {
mem_reg_rs2 := ex_rs2 mem_reg_rs2 := ex_rs2
} }
@ -294,7 +287,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
wb_reg_wdata := mem_ll_wdata wb_reg_wdata := mem_ll_wdata
} }
wb_wdata := Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword, wb_wdata := Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
Mux(io.ctrl.pcr != PCR.N, pcr.io.rw.rdata, Mux(io.ctrl.csr != CSR.N, pcr.io.rw.rdata,
wb_reg_wdata)) wb_reg_wdata))
when (wb_wen) { writeRF(wb_reg_waddr, wb_wdata) } when (wb_wen) { writeRF(wb_reg_waddr, wb_wdata) }
@ -305,8 +298,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.ctrl.fp_sboard_clra := dmem_resp_waddr io.ctrl.fp_sboard_clra := dmem_resp_waddr
// processor control regfile write // processor control regfile write
pcr.io.rw.addr := wb_reg_inst(19,15).toUInt pcr.io.rw.addr := wb_reg_inst(31,20)
pcr.io.rw.cmd := io.ctrl.pcr pcr.io.rw.cmd := io.ctrl.csr
pcr.io.rw.wdata := wb_reg_wdata pcr.io.rw.wdata := wb_reg_wdata
io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst) io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst)
@ -321,7 +314,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
wb_reg_pc)).toUInt // PC_WB wb_reg_pc)).toUInt // PC_WB
printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc, pcr.io.time(32,0), io.ctrl.retire, wb_reg_pc,
Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata, Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs1)), wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs1)),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs2)), wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs2)),

176
rocket/src/main/scala/dpath_util.scala
View File

@ -72,75 +72,47 @@ class Status extends Bundle {
val s = Bool() val s = Bool()
} }
object PCR object CSR
{ {
// commands // commands
val SZ = 3 val SZ = 2
val X = Bits("b???", 3) val X = Bits("b??", 2)
val N = Bits(0,3) val N = Bits(0,2)
val F = Bits(1,3) // mfpcr val W = Bits(1,2)
val T = Bits(4,3) // mtpcr val S = Bits(2,2)
val C = Bits(6,3) // clearpcr val C = Bits(3,2)
val S = Bits(7,3) // setpcr
// regs
val SUP0 = 0
val SUP1 = 1
val EPC = 2
val BADVADDR = 3
val PTBR = 4
val ASID = 5
val COUNT = 6
val COMPARE = 7
val EVEC = 8
val CAUSE = 9
val STATUS = 10
val HARTID = 11
val IMPL = 12
val FATC = 13
val SEND_IPI = 14
val CLR_IPI = 15
val STATS = 28
val RESET = 29
val TOHOST = 30
val FROMHOST = 31
} }
class PCR(implicit conf: RocketConfiguration) extends Module class CSRFile(implicit conf: RocketConfiguration) extends Module
{ {
val io = new Bundle { val io = new Bundle {
val host = new HTIFIO(conf.tl.ln.nClients) val host = new HTIFIO(conf.tl.ln.nClients)
val rw = new Bundle { val rw = new Bundle {
val addr = UInt(INPUT, log2Up(conf.nxpr)) val addr = UInt(INPUT, 12)
val cmd = Bits(INPUT, PCR.SZ) val cmd = Bits(INPUT, CSR.SZ)
val rdata = Bits(OUTPUT, conf.xprlen) val rdata = Bits(OUTPUT, conf.xprlen)
val wdata = Bits(INPUT, conf.xprlen) val wdata = Bits(INPUT, conf.xprlen)
} }
// there is a fixed constant related to this in PCRReq.addr
require(log2Up(conf.nxpr) == 5)
val status = new Status().asOutput val status = new Status().asOutput
val ptbr = UInt(OUTPUT, PADDR_BITS) val ptbr = UInt(OUTPUT, PADDR_BITS)
val evec = UInt(OUTPUT, VADDR_BITS+1) val evec = UInt(OUTPUT, VADDR_BITS+1)
val exception = Bool(INPUT) val exception = Bool(INPUT)
val retire = Bool(INPUT)
val cause = UInt(INPUT, 6) val cause = UInt(INPUT, 6)
val badvaddr_wen = Bool(INPUT) val badvaddr_wen = Bool(INPUT)
val pc = UInt(INPUT, VADDR_BITS+1) val pc = UInt(INPUT, VADDR_BITS+1)
val eret = Bool(INPUT) val sret = Bool(INPUT)
val ei = Bool(INPUT)
val di = Bool(INPUT)
val fatc = Bool(OUTPUT) val fatc = Bool(OUTPUT)
val irq_timer = Bool(OUTPUT)
val irq_ipi = Bool(OUTPUT)
val replay = Bool(OUTPUT) val replay = Bool(OUTPUT)
val time = UInt(OUTPUT, 64)
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
} }
import PCR._
val reg_epc = Reg(Bits(width = VADDR_BITS+1)) val reg_epc = Reg(Bits(width = VADDR_BITS+1))
val reg_badvaddr = Reg(Bits(width = VADDR_BITS)) val reg_badvaddr = Reg(Bits(width = VADDR_BITS))
val reg_evec = Reg(Bits(width = VADDR_BITS)) val reg_evec = Reg(Bits(width = VADDR_BITS))
val reg_count = WideCounter(32)
val reg_compare = Reg(Bits(width = 32)) val reg_compare = Reg(Bits(width = 32))
val reg_cause = Reg(Bits(width = io.cause.getWidth)) val reg_cause = Reg(Bits(width = io.cause.getWidth))
val reg_tohost = Reg(init=Bits(0, conf.xprlen)) val reg_tohost = Reg(init=Bits(0, conf.xprlen))
@ -150,12 +122,17 @@ class PCR(implicit conf: RocketConfiguration) extends Module
val reg_ptbr = Reg(UInt(width = PADDR_BITS)) val reg_ptbr = Reg(UInt(width = PADDR_BITS))
val reg_stats = Reg(init=Bool(false)) val reg_stats = Reg(init=Bool(false))
val reg_status = Reg(new Status) // reset down below val reg_status = Reg(new Status) // reset down below
val reg_time = WideCounter(64)
val reg_instret = WideCounter(64, io.retire)
val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3))
val r_irq_timer = Reg(init=Bool(false)) val r_irq_timer = Reg(init=Bool(false))
val r_irq_ipi = Reg(init=Bool(true)) val r_irq_ipi = Reg(init=Bool(true))
val cpu_req_valid = io.rw.cmd != CSR.N
val host_pcr_req_valid = Reg(Bool()) // don't reset val host_pcr_req_valid = Reg(Bool()) // don't reset
val host_pcr_req_fire = host_pcr_req_valid && io.rw.cmd === PCR.N val host_pcr_req_fire = host_pcr_req_valid && !cpu_req_valid
val host_pcr_rep_valid = Reg(Bool()) // don't reset val host_pcr_rep_valid = Reg(Bool()) // don't reset
val host_pcr_bits = Reg(io.host.pcr_req.bits) val host_pcr_bits = Reg(io.host.pcr_req.bits)
io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
@ -174,15 +151,26 @@ class PCR(implicit conf: RocketConfiguration) extends Module
io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
val addr = Mux(io.rw.cmd != PCR.N, io.rw.addr, host_pcr_bits.addr) val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500)
val wen = io.rw.cmd === PCR.T || io.rw.cmd === PCR.S || io.rw.cmd === PCR.C || val decoded_addr = {
host_pcr_req_fire && host_pcr_bits.rw val default = List(Bits("b" + ("?"*CSRs.all.size), CSRs.all.size))
val wdata = Mux(io.rw.cmd != PCR.N, io.rw.wdata, host_pcr_bits.data) val outs = for (i <- 0 until CSRs.all.size)
yield UInt(CSRs.all(i), addr.getWidth) -> List(UInt(BigInt(1) << i, CSRs.all.size))
val d = DecodeLogic(addr, default, outs).toArray
val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool])
for (i <- 0 until CSRs.all.size)
a(CSRs.all(i)) = d(0)(i)
a
}
val wen = cpu_req_valid || host_pcr_req_fire && host_pcr_bits.rw
val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data)
io.status := reg_status io.status := reg_status
io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false), io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
Bool(false), Bool(false), Bool(false), Bool(false)) Bool(false), Bool(false), Bool(false), Bool(false))
io.fatc := wen && addr === FATC io.fatc := wen && decoded_addr(CSRs.fatc)
io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
io.ptbr := reg_ptbr io.ptbr := reg_ptbr
@ -202,41 +190,64 @@ class PCR(implicit conf: RocketConfiguration) extends Module
reg_cause := io.cause reg_cause := io.cause
} }
when (io.eret) { when (io.sret) {
reg_status.s := reg_status.ps reg_status.s := reg_status.ps
reg_status.ei := reg_status.pei reg_status.ei := reg_status.pei
} }
when (reg_count === reg_compare) { when (reg_time(reg_compare.getWidth-1,0) === reg_compare) {
r_irq_timer := Bool(true); r_irq_timer := true
} }
io.irq_timer := r_irq_timer; io.time := reg_time
io.irq_ipi := r_irq_ipi; io.host.ipi_req.valid := cpu_req_valid && decoded_addr(CSRs.send_ipi)
io.host.ipi_req.valid := io.rw.cmd === PCR.T && io.rw.addr === SEND_IPI
io.host.ipi_req.bits := io.rw.wdata io.host.ipi_req.bits := io.rw.wdata
io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
when (host_pcr_req_fire && !host_pcr_bits.rw && host_pcr_bits.addr === TOHOST) { reg_tohost := UInt(0) } when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) }
val read_impl = Bits(2) val read_impl = Bits(2)
val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0) val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0)
io.rw.rdata := AVec[Bits](
reg_sup0, reg_sup1, reg_epc, reg_badvaddr, val read_mapping = Map[Int,Bits](
reg_ptbr, Bits(0)/*asid*/, reg_count, reg_compare, CSRs.fflags -> (if (conf.fpu) reg_fflags else UInt(0)),
reg_evec, reg_cause, io.status.toBits, io.host.id, CSRs.frm -> (if (conf.fpu) reg_frm else UInt(0)),
read_impl, read_impl/*x*/, read_impl/*x*/, read_impl/*x*/, CSRs.fcsr -> (if (conf.fpu) Cat(reg_frm, reg_fflags) else UInt(0)),
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, CSRs.cycle -> reg_time,
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, CSRs.time -> reg_time,
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, CSRs.instret -> reg_instret,
reg_stats, reg_fromhost/*x*/, reg_tohost, reg_fromhost CSRs.sup0 -> reg_sup0,
)(addr) CSRs.sup1 -> reg_sup1,
CSRs.epc -> reg_epc,
CSRs.badvaddr -> reg_badvaddr,
CSRs.ptbr -> read_ptbr,
CSRs.asid -> UInt(0),
CSRs.count -> reg_time,
CSRs.compare -> reg_compare,
CSRs.evec -> reg_evec,
CSRs.cause -> read_cause,
CSRs.status -> io.status.toBits,
CSRs.hartid -> io.host.id,
CSRs.impl -> read_impl,
CSRs.fatc -> read_impl, // don't care
CSRs.send_ipi -> read_impl, // don't care
CSRs.clear_ipi -> read_impl, // don't care
CSRs.stats -> reg_stats,
CSRs.tohost -> reg_tohost,
CSRs.fromhost -> reg_fromhost)
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
io.fcsr_rm := reg_frm
when (io.fcsr_flags.valid) {
reg_fflags := reg_fflags | io.fcsr_flags.bits
}
when (wen) { when (wen) {
when (addr === STATUS) { when (decoded_addr(CSRs.status)) {
val sr_wdata = Mux(io.rw.cmd === PCR.S, reg_status.toBits | wdata, val sr_wdata = Mux(io.rw.cmd === CSR.S, reg_status.toBits | wdata,
Mux(io.rw.cmd === PCR.C, reg_status.toBits & ~wdata, Mux(io.rw.cmd === CSR.C, reg_status.toBits & ~wdata,
wdata)) wdata))
reg_status := new Status().fromBits(sr_wdata) reg_status := new Status().fromBits(sr_wdata)
@ -247,17 +258,22 @@ class PCR(implicit conf: RocketConfiguration) extends Module
if (conf.rocc.isEmpty) reg_status.er := false if (conf.rocc.isEmpty) reg_status.er := false
if (!conf.fpu) reg_status.ef := false if (!conf.fpu) reg_status.ef := false
} }
when (addr === EPC) { reg_epc := wdata(VADDR_BITS,0).toSInt } when (io.rw.cmd != CSR.C && io.rw.cmd != CSR.S) {
when (addr === EVEC) { reg_evec := wdata(VADDR_BITS-1,0).toSInt } when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
when (addr === COUNT) { reg_count := wdata.toUInt } when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
when (addr === COMPARE) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false); } when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
when (addr === FROMHOST) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } } when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt }
when (addr === TOHOST) { when (reg_tohost === UInt(0)) { reg_tohost := wdata } } when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt }
when (addr === CLR_IPI) { r_irq_ipi := wdata(0) } when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
when (addr === SUP0) { reg_sup0 := wdata; } when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false); }
when (addr === SUP1) { reg_sup1 := wdata; } when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
when (addr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt; } when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0)) { reg_tohost := wdata } }
when (addr === STATS) { reg_stats := wdata(0) } when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata; }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata; }
when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt; }
when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
}
} }
io.host.ipi_rep.ready := Bool(true) io.host.ipi_rep.ready := Bool(true)

164
rocket/src/main/scala/fpu.scala
View File

@ -32,9 +32,7 @@ object FPConstants
val FCMD_MIN = Bits("b011000") val FCMD_MIN = Bits("b011000")
val FCMD_MAX = Bits("b011001") val FCMD_MAX = Bits("b011001")
val FCMD_MFTX = Bits("b011100") val FCMD_MFTX = Bits("b011100")
val FCMD_MFFSR = Bits("b011101")
val FCMD_MXTF = Bits("b011110") val FCMD_MXTF = Bits("b011110")
val FCMD_MTFSR = Bits("b011111")
val FCMD_MADD = Bits("b100100") val FCMD_MADD = Bits("b100100")
val FCMD_MSUB = Bits("b100101") val FCMD_MSUB = Bits("b100101")
val FCMD_NMSUB = Bits("b100110") val FCMD_NMSUB = Bits("b100110")
@ -43,7 +41,9 @@ object FPConstants
val FCMD_STORE = Bits("b111001") val FCMD_STORE = Bits("b111001")
val FCMD_X = Bits("b??????") val FCMD_X = Bits("b??????")
val FCMD_WIDTH = 6 val FCMD_WIDTH = 6
val FSR_WIDTH = 8
val RM_SZ = 3
val FLAGS_SZ = 5
} }
class FPUCtrlSigs extends Bundle class FPUCtrlSigs extends Bundle
@ -59,8 +59,6 @@ class FPUCtrlSigs extends Bundle
val fastpipe = Bool() val fastpipe = Bool()
val fma = Bool() val fma = Bool()
val round = Bool() val round = Bool()
val rdfsr = Bool()
val wrfsr = Bool()
} }
class FPUDecoder extends Module class FPUDecoder extends Module
@ -74,67 +72,65 @@ class FPUDecoder extends Module
val Y = Bool(true) val Y = Bool(true)
val X = Bool(false) val X = Bool(false)
val decoder = DecodeLogic(io.inst, val decoder = DecodeLogic(io.inst,
List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X), List (FCMD_X, X,X,X,X,X,X,X,X,X,X),
Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N,N,N), Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N),
FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N), FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N),
FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N,N,N), FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N),
FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N,N,N), FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N),
FMV_S_X -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,Y,N,N), FMV_S_X -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,Y),
FMV_D_X -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,Y,N,N), FMV_D_X -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,Y),
FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,Y),
FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,Y),
FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,Y),
FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,Y),
FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,Y),
FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,Y),
FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,Y),
FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y),
FMV_X_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y,N,N), FMV_X_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y),
FMV_X_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y,N,N), FMV_X_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y),
FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,Y),
FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,Y),
FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,Y),
FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,Y),
FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,Y,N,N), FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,Y),
FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,Y,N,N), FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,Y),
FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,Y),
FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,Y),
FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,Y),
FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,Y,N,N), FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,Y),
FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,Y,N,N), FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,Y),
FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,Y,N,N), FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,Y),
FSSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,Y), FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,Y),
FRSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,N), FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,Y),
FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,Y),
FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,Y),
FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,Y),
FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,Y),
FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,Y),
FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,Y),
FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,Y,N,N), FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,Y),
FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,Y,N,N), FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,Y),
FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,Y,N,N), FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,Y),
FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,Y,N,N), FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,Y),
FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,Y),
FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,Y),
FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,Y),
FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,Y),
FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,Y),
FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y),
FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,Y),
FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y),
FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,Y),
FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,Y),
FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N), FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,Y),
FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N), FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,Y)
FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N),
FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N)
)) ))
val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: round :: rdfsr :: wrfsr :: Nil = decoder val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: round :: Nil = decoder
io.sigs.cmd := cmd io.sigs.cmd := cmd
io.sigs.wen := wen.toBool io.sigs.wen := wen.toBool
@ -147,14 +143,15 @@ class FPUDecoder extends Module
io.sigs.fastpipe := fastpipe.toBool io.sigs.fastpipe := fastpipe.toBool
io.sigs.fma := fma.toBool io.sigs.fma := fma.toBool
io.sigs.round := round.toBool io.sigs.round := round.toBool
io.sigs.rdfsr := rdfsr.toBool
io.sigs.wrfsr := wrfsr.toBool
} }
class DpathFPUIO extends Bundle { class DpathFPUIO extends Bundle {
val inst = Bits(OUTPUT, 32) val inst = Bits(OUTPUT, 32)
val fromint_data = Bits(OUTPUT, 64) val fromint_data = Bits(OUTPUT, 64)
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
val store_data = Bits(INPUT, 64) val store_data = Bits(INPUT, 64)
val toint_data = Bits(INPUT, 64) val toint_data = Bits(INPUT, 64)
@ -166,6 +163,7 @@ class DpathFPUIO extends Bundle {
class CtrlFPUIO extends Bundle { class CtrlFPUIO extends Bundle {
val valid = Bool(OUTPUT) val valid = Bool(OUTPUT)
val fcsr_rdy = Bool(INPUT)
val nack_mem = Bool(INPUT) val nack_mem = Bool(INPUT)
val illegal_rm = Bool(INPUT) val illegal_rm = Bool(INPUT)
val killx = Bool(OUTPUT) val killx = Bool(OUTPUT)
@ -182,7 +180,6 @@ class FPToInt extends Module
val single = Bool() val single = Bool()
val cmd = Bits(width = FCMD_WIDTH) val cmd = Bits(width = FCMD_WIDTH)
val rm = Bits(width = 3) val rm = Bits(width = 3)
val fsr = Bits(width = FSR_WIDTH)
val in1 = Bits(width = 65) val in1 = Bits(width = 65)
val in2 = Bits(width = 65) val in2 = Bits(width = 65)
override def clone = new Input().asInstanceOf[this.type] override def clone = new Input().asInstanceOf[this.type]
@ -211,7 +208,6 @@ class FPToInt extends Module
in.single := io.in.bits.single in.single := io.in.bits.single
in.cmd := io.in.bits.cmd in.cmd := io.in.bits.cmd
in.rm := io.in.bits.rm in.rm := io.in.bits.rm
in.fsr := io.in.bits.fsr
} }
val unrec_s = hardfloat.recodedFloatNToFloatN(in.in1, 23, 9) val unrec_s = hardfloat.recodedFloatNToFloatN(in.in1, 23, 9)
@ -228,9 +224,6 @@ class FPToInt extends Module
io.out.bits.toint := Mux(in.single, Cat(Fill(32, unrec_s(31)), unrec_s), unrec_d) io.out.bits.toint := Mux(in.single, Cat(Fill(32, unrec_s(31)), unrec_s), unrec_d)
io.out.bits.exc := Bits(0) io.out.bits.exc := Bits(0)
when (in.cmd === FCMD_MTFSR || in.cmd === FCMD_MFFSR) {
io.out.bits.toint := io.in.bits.fsr
}
when (in.cmd === FCMD_CVT_W_FMT || in.cmd === FCMD_CVT_WU_FMT) { when (in.cmd === FCMD_CVT_W_FMT || in.cmd === FCMD_CVT_WU_FMT) {
io.out.bits.toint := Cat(Fill(32, d2i._1(31)), d2i._1(31,0)) io.out.bits.toint := Cat(Fill(32, d2i._1(31)), d2i._1(31,0))
io.out.bits.exc := d2i._2 io.out.bits.exc := d2i._2
@ -472,9 +465,6 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module
val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12) val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12)
val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1), rec_s), rec_d) val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1), rec_s), rec_d)
val fsr_rm = Reg(Bits(width = 3))
val fsr_exc = Reg(Bits(width = 5))
// regfile // regfile
val regfile = Mem(Bits(width = 65), 32) val regfile = Mem(Bits(width = 65), 32)
when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded } when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded }
@ -482,13 +472,12 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module
val ex_rs1 = regfile(ex_reg_inst(19,15)) val ex_rs1 = regfile(ex_reg_inst(19,15))
val ex_rs2 = regfile(ex_reg_inst(24,20)) val ex_rs2 = regfile(ex_reg_inst(24,20))
val ex_rs3 = regfile(ex_reg_inst(31,27)) val ex_rs3 = regfile(ex_reg_inst(31,27))
val ex_rm = Mux(ex_reg_inst(14,12) === Bits(7), fsr_rm, ex_reg_inst(14,12)) val ex_rm = Mux(ex_reg_inst(14,12) === Bits(7), io.dpath.fcsr_rm, ex_reg_inst(14,12))
val fpiu = Module(new FPToInt) val fpiu = Module(new FPToInt)
fpiu.io.in.valid := ex_reg_valid && ctrl.toint fpiu.io.in.valid := ex_reg_valid && ctrl.toint
fpiu.io.in.bits := ctrl fpiu.io.in.bits := ctrl
fpiu.io.in.bits.rm := ex_rm fpiu.io.in.bits.rm := ex_rm
fpiu.io.in.bits.fsr := Cat(fsr_rm, fsr_exc)
fpiu.io.in.bits.in1 := ex_rs1 fpiu.io.in.bits.in1 := ex_rs1
fpiu.io.in.bits.in2 := ex_rs2 fpiu.io.in.bits.in2 := ex_rs2
@ -576,24 +565,17 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module
val wexc = Vec(pipes.map(_.wexc))(wsrc) val wexc = Vec(pipes.map(_.wexc))(wsrc)
when (wen(0)) { regfile(waddr(4,0)) := wdata } when (wen(0)) { regfile(waddr(4,0)) := wdata }
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
when (wb_reg_valid && wb_ctrl.toint || wen(0)) { io.dpath.fcsr_flags.valid := wb_toint_valid || wen(0)
fsr_exc := fsr_exc | io.dpath.fcsr_flags.bits :=
Fill(fsr_exc.getWidth, wb_reg_valid && wb_ctrl.toint) & wb_toint_exc | Mux(wb_toint_valid, wb_toint_exc, UInt(0)) |
Fill(fsr_exc.getWidth, wen(0)) & wexc Mux(wen(0), wexc, UInt(0))
}
val mem_fsr_wdata = RegEnable(io.dpath.fromint_data(FSR_WIDTH-1,0), ex_reg_valid && ctrl.wrfsr)
val wb_fsr_wdata = RegEnable(mem_fsr_wdata, mem_reg_valid && mem_ctrl.wrfsr)
when (wb_reg_valid && wb_ctrl.wrfsr) {
fsr_exc := wb_fsr_wdata
fsr_rm := wb_fsr_wdata >> fsr_exc.getWidth
}
val fp_inflight = wb_reg_valid && wb_ctrl.toint || wen.orR val fp_inflight = wb_reg_valid && wb_ctrl.toint || wen.orR
val fsr_busy = mem_ctrl.rdfsr && fp_inflight || wb_reg_valid && wb_ctrl.wrfsr
val units_busy = mem_reg_valid && mem_ctrl.fma && Reg(next=Mux(ctrl.single, io.sfma.valid, io.dfma.valid)) val units_busy = mem_reg_valid && mem_ctrl.fma && Reg(next=Mux(ctrl.single, io.sfma.valid, io.dfma.valid))
io.ctrl.nack_mem := fsr_busy || units_busy || write_port_busy io.ctrl.fcsr_rdy := !fp_inflight
io.ctrl.nack_mem := units_busy || write_port_busy
io.ctrl.dec <> fp_decoder.io.sigs io.ctrl.dec <> fp_decoder.io.sigs
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(Bool(false))(_||_) def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(Bool(false))(_||_)
io.ctrl.sboard_set := wb_reg_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl))) io.ctrl.sboard_set := wb_reg_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl)))

115
rocket/src/main/scala/instructions.scala
View File

@ -3,9 +3,8 @@ package rocket
import Chisel._ import Chisel._
import Node._ import Node._
object Instructions /* Automatically generated by parse-opcodes */
{ object Instructions {
/* Automatically generated by parse-opcodes */
def JAL = Bits("b?????????????????????????1100111") def JAL = Bits("b?????????????????????????1100111")
def JALR = Bits("b?????????????????000?????1101111") def JALR = Bits("b?????????????????000?????1101111")
def BEQ = Bits("b?????????????????000?????1100011") def BEQ = Bits("b?????????????????000?????1100011")
@ -35,14 +34,6 @@ object Instructions
def SRA = Bits("b0100000??????????101?????0110011") def SRA = Bits("b0100000??????????101?????0110011")
def OR = Bits("b0000000??????????110?????0110011") def OR = Bits("b0000000??????????110?????0110011")
def AND = Bits("b0000000??????????111?????0110011") def AND = Bits("b0000000??????????111?????0110011")
def MUL = Bits("b0000001??????????000?????0110011")
def MULH = Bits("b0000001??????????001?????0110011")
def MULHSU = Bits("b0000001??????????010?????0110011")
def MULHU = Bits("b0000001??????????011?????0110011")
def DIV = Bits("b0000001??????????100?????0110011")
def DIVU = Bits("b0000001??????????101?????0110011")
def REM = Bits("b0000001??????????110?????0110011")
def REMU = Bits("b0000001??????????111?????0110011")
def ADDIW = Bits("b?????????????????000?????0011011") def ADDIW = Bits("b?????????????????000?????0011011")
def SLLIW = Bits("b0000000??????????001?????0011011") def SLLIW = Bits("b0000000??????????001?????0011011")
def SRLIW = Bits("b0000000??????????101?????0011011") def SRLIW = Bits("b0000000??????????101?????0011011")
@ -52,11 +43,6 @@ object Instructions
def SLLW = Bits("b0000000??????????001?????0111011") def SLLW = Bits("b0000000??????????001?????0111011")
def SRLW = Bits("b0000000??????????101?????0111011") def SRLW = Bits("b0000000??????????101?????0111011")
def SRAW = Bits("b0100000??????????101?????0111011") def SRAW = Bits("b0100000??????????101?????0111011")
def MULW = Bits("b0000001??????????000?????0111011")
def DIVW = Bits("b0000001??????????100?????0111011")
def DIVUW = Bits("b0000001??????????101?????0111011")
def REMW = Bits("b0000001??????????110?????0111011")
def REMUW = Bits("b0000001??????????111?????0111011")
def LB = Bits("b?????????????????000?????0000011") def LB = Bits("b?????????????????000?????0000011")
def LH = Bits("b?????????????????001?????0000011") def LH = Bits("b?????????????????001?????0000011")
def LW = Bits("b?????????????????010?????0000011") def LW = Bits("b?????????????????010?????0000011")
@ -68,6 +54,21 @@ object Instructions
def SH = Bits("b?????????????????001?????0100011") def SH = Bits("b?????????????????001?????0100011")
def SW = Bits("b?????????????????010?????0100011") def SW = Bits("b?????????????????010?????0100011")
def SD = Bits("b?????????????????011?????0100011") def SD = Bits("b?????????????????011?????0100011")
def FENCE = Bits("b?????????????????000?????0001111")
def FENCE_I = Bits("b?????????????????001?????0001111")
def MUL = Bits("b0000001??????????000?????0110011")
def MULH = Bits("b0000001??????????001?????0110011")
def MULHSU = Bits("b0000001??????????010?????0110011")
def MULHU = Bits("b0000001??????????011?????0110011")
def DIV = Bits("b0000001??????????100?????0110011")
def DIVU = Bits("b0000001??????????101?????0110011")
def REM = Bits("b0000001??????????110?????0110011")
def REMU = Bits("b0000001??????????111?????0110011")
def MULW = Bits("b0000001??????????000?????0111011")
def DIVW = Bits("b0000001??????????100?????0111011")
def DIVUW = Bits("b0000001??????????101?????0111011")
def REMW = Bits("b0000001??????????110?????0111011")
def REMUW = Bits("b0000001??????????111?????0111011")
def AMOADD_W = Bits("b00000????????????010?????0101111") def AMOADD_W = Bits("b00000????????????010?????0101111")
def AMOXOR_W = Bits("b00100????????????010?????0101111") def AMOXOR_W = Bits("b00100????????????010?????0101111")
def AMOOR_W = Bits("b01000????????????010?????0101111") def AMOOR_W = Bits("b01000????????????010?????0101111")
@ -90,18 +91,15 @@ object Instructions
def AMOSWAP_D = Bits("b00001????????????011?????0101111") def AMOSWAP_D = Bits("b00001????????????011?????0101111")
def LR_D = Bits("b00010??00000?????011?????0101111") def LR_D = Bits("b00010??00000?????011?????0101111")
def SC_D = Bits("b00011????????????011?????0101111") def SC_D = Bits("b00011????????????011?????0101111")
def FENCE = Bits("b?????????????????000?????0001111") def SCALL = Bits("b00000000000000000000000001110011")
def FENCE_I = Bits("b?????????????????001?????0001111") def SBREAK = Bits("b00000000000100000000000001110011")
def SYSCALL = Bits("b00000000000000000000000001110111") def SRET = Bits("b10000000000000000000000001110011")
def BREAK = Bits("b00000000000000000001000001110111") def CSRRW = Bits("b?????????????????001?????1110011")
def RDCYCLE = Bits("b00000000000000000100?????1110111") def CSRRS = Bits("b?????????????????010?????1110011")
def RDTIME = Bits("b00000010000000000100?????1110111") def CSRRC = Bits("b?????????????????011?????1110011")
def RDINSTRET = Bits("b00000100000000000100?????1110111") def CSRRWI = Bits("b?????????????????101?????1110011")
def MTPCR = Bits("b0000000??????????000?????1110011") def CSRRSI = Bits("b?????????????????110?????1110011")
def MFPCR = Bits("b000000000000?????001?????1110011") def CSRRCI = Bits("b?????????????????111?????1110011")
def SETPCR = Bits("b?????????????????010?????1110011")
def CLEARPCR = Bits("b?????????????????011?????1110011")
def ERET = Bits("b00000000000000000100000001110011")
def FADD_S = Bits("b0000000??????????????????1010011") def FADD_S = Bits("b0000000??????????????????1010011")
def FSUB_S = Bits("b0000100??????????????????1010011") def FSUB_S = Bits("b0000100??????????????????1010011")
def FMUL_S = Bits("b0001000??????????????????1010011") def FMUL_S = Bits("b0001000??????????????????1010011")
@ -148,10 +146,8 @@ object Instructions
def FMAX_D = Bits("b1100101??????????000?????1010011") def FMAX_D = Bits("b1100101??????????000?????1010011")
def FMV_X_S = Bits("b111000000000?????000?????1010011") def FMV_X_S = Bits("b111000000000?????000?????1010011")
def FMV_X_D = Bits("b111000100000?????000?????1010011") def FMV_X_D = Bits("b111000100000?????000?????1010011")
def FRSR = Bits("b11101000000000000000?????1010011")
def FMV_S_X = Bits("b111100000000?????000?????1010011") def FMV_S_X = Bits("b111100000000?????000?????1010011")
def FMV_D_X = Bits("b111100100000?????000?????1010011") def FMV_D_X = Bits("b111100100000?????000?????1010011")
def FSSR = Bits("b111110000000?????000?????1010011")
def FLW = Bits("b?????????????????010?????0000111") def FLW = Bits("b?????????????????010?????0000111")
def FLD = Bits("b?????????????????011?????0000111") def FLD = Bits("b?????????????????011?????0000111")
def FSW = Bits("b?????????????????010?????0100111") def FSW = Bits("b?????????????????010?????0100111")
@ -164,7 +160,6 @@ object Instructions
def FMSUB_D = Bits("b?????01??????????????????1000111") def FMSUB_D = Bits("b?????01??????????????????1000111")
def FNMSUB_D = Bits("b?????01??????????????????1001011") def FNMSUB_D = Bits("b?????01??????????????????1001011")
def FNMADD_D = Bits("b?????01??????????????????1001111") def FNMADD_D = Bits("b?????01??????????????????1001111")
/* Automatically generated by parse-opcodes */
def CUSTOM0 = Bits("b?????????????????000?????0001011") def CUSTOM0 = Bits("b?????????????????000?????0001011")
def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011") def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011")
def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011") def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011")
@ -190,3 +185,61 @@ object Instructions
def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011") def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011")
def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011") def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
} }
object CSRs {
val sup0 = 1280
val fflags = 1
val frm = 2
val fcsr = 3
val cycle = 4
val time = 5
val instret = 6
val sup1 = 1281
val evec = 1288
val cause = 1289
val status = 1290
val hartid = 1291
val impl = 1292
val epc = 1282
val send_ipi = 1294
val clear_ipi = 1295
val badvaddr = 1283
val ptbr = 1284
val stats = 1308
val reset = 1309
val tohost = 1310
val asid = 1285
val count = 1286
val compare = 1287
val fromhost = 1311
val fatc = 1293
val all = {
val res = collection.mutable.ArrayBuffer[Int]()
res += sup0
res += fflags
res += frm
res += fcsr
res += cycle
res += time
res += instret
res += sup1
res += evec
res += cause
res += status
res += hartid
res += impl
res += epc
res += send_ipi
res += clear_ipi
res += badvaddr
res += ptbr
res += stats
res += reset
res += tohost
res += asid
res += count
res += compare
res += fromhost
res += fatc
res.toArray
}
}

2
rocket/src/main/scala/nbdcache.scala
View File

@ -881,7 +881,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
lrsc_count := 0 lrsc_count := 0
} }
} }
when (io.cpu.ptw.eret) { lrsc_count := 0 } when (io.cpu.ptw.sret) { lrsc_count := 0 }
val s2_data = Vec.fill(conf.ways){Bits(width = conf.bitsperrow)} val s2_data = Vec.fill(conf.ways){Bits(width = conf.bitsperrow)}
for (w <- 0 until conf.ways) { for (w <- 0 until conf.ways) {

6
rocket/src/main/scala/ptw.scala
View File

@ -17,13 +17,13 @@ class TLBPTWIO extends Bundle {
val status = new Status().asInput val status = new Status().asInput
val invalidate = Bool(INPUT) val invalidate = Bool(INPUT)
val eret = Bool(INPUT) val sret = Bool(INPUT)
} }
class DatapathPTWIO extends Bundle { class DatapathPTWIO extends Bundle {
val ptbr = UInt(INPUT, PADDR_BITS) val ptbr = UInt(INPUT, PADDR_BITS)
val invalidate = Bool(INPUT) val invalidate = Bool(INPUT)
val eret = Bool(INPUT) val sret = Bool(INPUT)
val status = new Status().asInput val status = new Status().asInput
} }
@ -83,7 +83,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
io.requestor(i).resp.bits.perm := r_pte(8,3) io.requestor(i).resp.bits.perm := r_pte(8,3)
io.requestor(i).resp.bits.ppn := resp_ppn.toUInt io.requestor(i).resp.bits.ppn := resp_ppn.toUInt
io.requestor(i).invalidate := io.dpath.invalidate io.requestor(i).invalidate := io.dpath.invalidate
io.requestor(i).eret := io.dpath.eret io.requestor(i).sret := io.dpath.sret
io.requestor(i).status := io.dpath.status io.requestor(i).status := io.dpath.status
} }