riscv/rocket-chip
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Update to new privileged ISA... phew

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This commit is contained in:
Andrew Waterman
2013-11-25 04:35:15 -08:00
parent 65b8340cea
commit 924261e2b2
8 changed files with 534 additions and 484 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@@ -881,7 +881,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
lrsc_count := 0
}
}
when (io.cpu.ptw.eret) { lrsc_count := 0 }
when (io.cpu.ptw.sret) { lrsc_count := 0 }
val s2_data = Vec.fill(conf.ways){Bits(width = conf.bitsperrow)}
for (w <- 0 until conf.ways) {