Update to new privileged ISA... phew
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@@ -881,7 +881,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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lrsc_count := 0
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}
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}
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when (io.cpu.ptw.eret) { lrsc_count := 0 }
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when (io.cpu.ptw.sret) { lrsc_count := 0 }
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val s2_data = Vec.fill(conf.ways){Bits(width = conf.bitsperrow)}
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for (w <- 0 until conf.ways) {
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