riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

local_interrupts: Correct off-by-1 if there is no SEIP

Browse Source
This commit is contained in:
Megan Wachs 2017-05-02 19:24:19 -07:00
parent 1ecd63611f
commit 922a8ef5e0
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/tile/Interrupts.scala
View File

@ -50,11 +50,12 @@ trait HasExternalInterruptsModule {
val periph_ips = Seq( val periph_ips = Seq(
core.msip, core.msip,
core.mtip, core.mtip,
core.meip, core.meip)
core.seip.getOrElse(Wire(Bool())))
val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil
val core_ips = core.lip val core_ips = core.lip
(async_ips ++ periph_ips ++ core_ips).zip(io.interrupts(0)).foreach { case(c, i) => c := i } (async_ips ++ periph_ips ++ seip ++ core_ips).zip(io.interrupts(0)).foreach { case(c, i) => c := i }
} }
} }