diplomacy: change API to auto-create node bundles => cross-module refs
This commit is contained in:
Wesley W. Terpstra
@ -13,12 +13,7 @@ class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyM
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val node = TLAsyncSourceNode(sync)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val sink_reset_n = out.a.sink_reset_n
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val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
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val depth = edgeOut.manager.depth
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@ -47,12 +42,7 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters)
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val node = TLAsyncSinkNode(depth, sync)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val source_reset_n = in.a.source_reset_n
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val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe
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@ -97,8 +87,8 @@ object TLAsyncCrossingSink
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class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val nodeIn = TLInputNode()
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val nodeOut = TLOutputNode()
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val nodeIn = TLIdentityNode()
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val nodeOut = TLIdentityNode()
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val node = NodeHandle(nodeIn, nodeOut)
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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@ -109,14 +99,12 @@ class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) ext
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val out = (nodeOut := sink.node)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = nodeIn.bundleIn
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val io = IO(new Bundle {
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val in_clock = Clock(INPUT)
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val in_reset = Bool(INPUT)
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val out = nodeOut.bundleOut
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val out_clock = Clock(INPUT)
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val out_reset = Bool(INPUT)
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}
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})
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source.module.clock := io.in_clock
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source.module.reset := io.in_reset
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@ -147,7 +135,7 @@ class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
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cross.node := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
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val monitor = (ram.node := cross.node)
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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// Shove the RAM into another clock domain
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@ -29,12 +29,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
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})})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val managers = edgeOut.manager.managers
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val beatBytes = edgeOut.manager.beatBytes
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@ -297,7 +292,7 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule
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model.node := fuzz.node
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ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLAtomicAutomata()(TLDelayer(0.1)(model.node))))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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}
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}
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@ -53,12 +53,7 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
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)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val clients = edgeIn.client.clients
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val managers = edgeOut.manager.managers
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val lineShift = log2Ceil(lineBytes)
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@ -35,12 +35,7 @@ class TLBuffer(
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val node = new TLBufferNode(a, b, c, d, e)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out.a <> a(in .a)
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in .d <> d(out.d)
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@ -80,8 +75,8 @@ object TLBuffer
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class TLBufferChain(depth: Int)(implicit p: Parameters) extends LazyModule {
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val nodeIn = TLInputNode()
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val nodeOut = TLOutputNode()
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val nodeIn = TLIdentityNode()
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val nodeOut = TLIdentityNode()
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val node = NodeHandle(nodeIn, nodeOut)
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val buf_chain = if (depth > 0) {
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@ -96,12 +91,7 @@ class TLBufferChain(depth: Int)(implicit p: Parameters) extends LazyModule {
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buf_chain.head.node :=? nodeIn
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nodeOut :=? buf_chain.last.node
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = nodeIn.bundleIn
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val out = nodeOut.bundleOut
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}
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}
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lazy val module = new LazyModuleImp(this) { }
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}
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object TLBufferChain
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@ -24,12 +24,7 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
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supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.supportsAcquireT)})})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val clients = edgeIn.client.clients
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val caches = clients.filter(_.supportsProbe)
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require (clients.size == 1 || caches.size == 0 || unsafe, "Only one client can safely use a TLCacheCork")
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@ -10,15 +10,10 @@ import freechips.rocketchip.diplomacy._
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// q is the probability to delay a request
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class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
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{
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val node = TLIdentityNode()
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val node = TLAdapterNode()
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require (0.0 <= q && q < 1)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T], noise: T) {
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val allow = UInt((q * 65535.0).toInt) <= LFSR16(source.valid)
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sink.valid := source.valid && allow
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@ -27,7 +22,7 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
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when (!sink.valid) { sink.bits := noise }
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}
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(io.in zip io.out) foreach { case (in, out) =>
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(node.in zip node.out) foreach { case ((in, _), (out, _)) =>
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val anoise = Wire(in.a.bits)
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anoise.opcode := LFSRNoiseMaker(3)
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anoise.param := LFSRNoiseMaker(3)
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@ -4,13 +4,15 @@ package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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class TLEdge(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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extends TLEdgeParameters(client, manager)
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manager: TLManagerPortParameters,
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params: Parameters)
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extends TLEdgeParameters(client, manager, params)
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{
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def isAligned(address: UInt, lgSize: UInt): Bool = {
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if (maxLgSize == 0) Bool(true) else {
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@ -262,8 +264,9 @@ class TLEdge(
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class TLEdgeOut(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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extends TLEdge(client, manager)
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manager: TLManagerPortParameters,
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params: Parameters)
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extends TLEdge(client, manager, params)
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{
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// Transfers
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def Acquire(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
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@ -476,8 +479,9 @@ class TLEdgeOut(
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class TLEdgeIn(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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extends TLEdge(client, manager)
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manager: TLManagerPortParameters,
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params: Parameters)
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extends TLEdge(client, manager, params)
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{
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// Transfers
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def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
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@ -41,12 +41,7 @@ class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Para
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})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
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// Do we need to serialize the request to this manager?
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@ -49,11 +49,9 @@ class TLFilter(
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})})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out <> in
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}
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io.out <> io.in
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}
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}
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@ -52,12 +52,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
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managerFn = { m => m.copy(managers = m.managers.map(mapManager)) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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// All managers must share a common FIFO domain (responses might end up interleaved)
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val manager = edgeOut.manager
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val managers = manager.managers
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@ -249,7 +244,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
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val aFrag = Mux(aOrig > limit, limit, aOrig)
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val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
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val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
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val aHasData = node.edgesIn(0).hasData(in_a.bits)
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val aHasData = edgeIn.hasData(in_a.bits)
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val aMask = Mux(aHasData, UInt(0), aFragOH1)
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val gennum = RegInit(UInt(0, width = counterBits))
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@ -317,7 +312,7 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa
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TLBuffer(BufferParams.flow)(
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model.node)))))))))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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}
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}
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@ -107,13 +107,11 @@ class TLFuzzer(
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val node = TLClientNode(Seq(TLClientPortParameters(clientParams)))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val out = node.bundleOut
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val io = IO(new Bundle {
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val finished = Bool(OUTPUT)
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}
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})
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val out = io.out(0)
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val edge = node.edgesOut(0)
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val (out, edge) = node.out(0)
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// Extract useful parameters from the TL edge
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val maxTransfer = edge.manager.maxTransfer
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@ -245,7 +243,7 @@ class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
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val monitor = (ram.node := cross.node)
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gpio.node := TLFragmenter(4, 32)(TLBuffer()(xbar.node))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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// Shove the RAM into another clock domain
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@ -16,12 +16,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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managerFn = { m => if (!supportManagers) m else m.copy(minLatency = min(1, m.minLatency), managers = m.managers.map(_.copy(supportsHint = TransferSizes(1, m.maxTransfer)))) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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// Don't add support for clients if there is no BCE channel
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val bce = edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
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require (!supportClients || bce)
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@ -118,7 +113,7 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
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model.node := fuzz.node
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ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLHintHandler()(TLDelayer(0.1)(model.node))))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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}
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}
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@ -61,12 +61,12 @@ object IntSinkPortSimple
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Seq.fill(ports)(IntSinkPortParameters(Seq.fill(sinks)(IntSinkParameters())))
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}
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case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters)
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case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters, params: Parameters)
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object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
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{
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def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu)
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def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu)
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def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters): IntEdge = IntEdge(pd, pu, p)
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def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters): IntEdge = IntEdge(pd, pu, p)
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def bundleO(eo: IntEdge): Vec[Bool] = Vec(eo.source.num, Bool())
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def bundleI(ei: IntEdge): Vec[Bool] = Vec(ei.source.num, Bool())
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@ -75,22 +75,21 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
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override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString
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override def labelO(eo: IntEdge) = eo.source.sources.map(_.range.size).sum.toString
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def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => {
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// Cannot use bulk connect, because the widths could differ
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(bo zip bi) foreach { case (o, i) => i := o }
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})
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}
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override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSourcePortParameters =
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pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) })
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override def mixI(pu: IntSinkPortParameters, node: InwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSinkPortParameters =
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pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
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}
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case class IntIdentityNode()(implicit valName: ValName) extends IdentityNode(IntImp)
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case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams)
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case class IntSinkNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends SinkNode(IntImp)(portParams)
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case class IntAdapterNode(
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sourceFn: IntSourcePortParameters => IntSourcePortParameters = { s => s },
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sinkFn: IntSinkPortParameters => IntSinkPortParameters = { s => s },
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num: Range.Inclusive = 0 to 999)(
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implicit valName: ValName)
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extends AdapterNode(IntImp)(sourceFn, sinkFn, num)
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case class IntIdentityNode()(implicit valName: ValName) extends IdentityNode(IntImp)()
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case class IntNexusNode(
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sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
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@ -100,15 +99,6 @@ case class IntNexusNode(
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implicit valName: ValName)
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extends NexusNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts)
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case class IntOutputNode()(implicit valName: ValName) extends OutputNode(IntImp)
|
||||
case class IntInputNode()(implicit valName: ValName) extends InputNode(IntImp)
|
||||
|
||||
case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends BlindOutputNode(IntImp)(portParams)
|
||||
case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends BlindInputNode(IntImp)(portParams)
|
||||
|
||||
case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends InternalOutputNode(IntImp)(portParams)
|
||||
case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends InternalInputNode(IntImp)(portParams)
|
||||
|
||||
class IntXbar()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val intnode = IntNexusNode(
|
||||
@ -120,27 +110,17 @@ class IntXbar()(implicit p: Parameters) extends LazyModule
|
||||
})
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = intnode.bundleIn
|
||||
val out = intnode.bundleOut
|
||||
}
|
||||
|
||||
val cat = (intnode.edgesIn zip io.in).map{ case (e, i) => i.take(e.source.num) }.flatten
|
||||
io.out.foreach { _ := cat }
|
||||
val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
|
||||
intnode.out.foreach { case (o, _) => o := cat }
|
||||
}
|
||||
}
|
||||
|
||||
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val intnode = IntIdentityNode()
|
||||
val intnode = IntAdapterNode()
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = intnode.bundleIn
|
||||
val out = intnode.bundleOut
|
||||
}
|
||||
|
||||
(io.in zip io.out) foreach { case (in, out) =>
|
||||
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
|
||||
out := SynchronizerShiftReg(in, sync)
|
||||
}
|
||||
}
|
||||
|
||||
@ -11,15 +11,13 @@ import freechips.rocketchip.util.AsyncBundle
|
||||
// READ the comments in the TLIsolation object before you instantiate this module
|
||||
class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLAsyncIdentityNode()
|
||||
val node = TLAsyncAdapterNode()
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
val io = IO(new Bundle {
|
||||
val iso_out = Bool(INPUT) // Isolate from client to manager
|
||||
val iso_in = Bool(INPUT) // Isolate from manager to client
|
||||
}
|
||||
})
|
||||
|
||||
def ISOo[T <: Data](x: T): T = x.fromBits(fOut(io.iso_out, x.asUInt))
|
||||
def ISOi[T <: Data](x: T): T = x.fromBits(fIn (io.iso_in, x.asUInt))
|
||||
@ -53,7 +51,7 @@ class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implici
|
||||
y.sink_reset_n := Bool(false)
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
ABo(out.a, in .a)
|
||||
ABi(in .d, out.d)
|
||||
|
||||
|
||||
@ -20,14 +20,8 @@ class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule
|
||||
AddressSet(fn(a), a.mask)))))})
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
io.out <> io.in
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
out <> in
|
||||
val convert = edgeIn.manager.managers.flatMap(_.address) zip edgeOut.manager.managers.flatMap(_.address)
|
||||
def forward(x: UInt) =
|
||||
convert.map { case (i, o) => Mux(i.contains(x), UInt(o.base) | (x & UInt(o.mask)), UInt(0)) }.reduce(_ | _)
|
||||
|
||||
@ -16,9 +16,9 @@ abstract class TLMonitorBase(args: TLMonitorArgs) extends MonitorBase()(args.sou
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val edges = args.edge()
|
||||
val io = new Bundle {
|
||||
val io = IO(new Bundle {
|
||||
val in = HeterogeneousBag(edges.map(p => new TLBundleSnoop(p.bundle))).flip
|
||||
}
|
||||
})
|
||||
|
||||
(edges zip io.in).foreach { case (e, in) => legalize(in, e, reset) }
|
||||
}
|
||||
|
||||
@ -9,9 +9,6 @@ import freechips.rocketchip.diplomacy._
|
||||
|
||||
case class TLNodeNumbererNode(nodeAddressOffset: Option[Int] = None)(implicit valName: ValName) extends TLCustomNode(0 to 999, 0 to 999)
|
||||
{
|
||||
val externalIn = true
|
||||
val externalOut = true
|
||||
|
||||
def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
|
||||
require (oStars + iStars <= 1, s"${name} (a custom adapter) appears left of a :*= ${iStars} times and right of a :=* ${oStars} times; at most once is allowed${lazyModule.line}")
|
||||
if (oStars > 0) {
|
||||
@ -46,15 +43,10 @@ class TLNodeNumberer(nodeAddressOffset: Option[Int] = None)(implicit p: Paramete
|
||||
val node = TLNodeNumbererNode(nodeAddressOffset)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
val minNodeOffset = log2Ceil(node.edgesOut.map(_.manager.maxAddress).max)
|
||||
val minNodeOffset = log2Ceil(node.out.map(_._2.manager.maxAddress).max)
|
||||
val nodeOffset = nodeAddressOffset.getOrElse(minNodeOffset)
|
||||
|
||||
(io.in zip io.out).zipWithIndex foreach { case ((in, out), i) =>
|
||||
(node.in zip node.out).zipWithIndex foreach { case (((in, _), (out, _)), i) =>
|
||||
out <> in
|
||||
// a&c address already get truncated
|
||||
in.b.bits.address := (UInt(i+1) << nodeOffset) | out.b.bits.address
|
||||
|
||||
@ -14,8 +14,8 @@ case object TLCombinationalCheck extends Field[Boolean](false)
|
||||
|
||||
object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
|
||||
{
|
||||
def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
|
||||
def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu)
|
||||
def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters): TLEdgeOut = new TLEdgeOut(pd, pu, p)
|
||||
def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters): TLEdgeIn = new TLEdgeIn(pd, pu, p)
|
||||
|
||||
def bundleO(eo: TLEdgeOut): TLBundle = TLBundle(eo.bundle)
|
||||
def bundleI(ei: TLEdgeIn): TLBundle = TLBundle(ei.bundle)
|
||||
@ -63,30 +63,18 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
|
||||
}
|
||||
}
|
||||
|
||||
// Nodes implemented inside modules
|
||||
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)
|
||||
case class TLClientNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams)
|
||||
case class TLManagerNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams)
|
||||
|
||||
object TLClientNode
|
||||
{
|
||||
def apply(params: TLClientParameters)(implicit valName: ValName) =
|
||||
new TLClientNode(Seq(TLClientPortParameters(Seq(params))))
|
||||
}
|
||||
|
||||
object TLManagerNode
|
||||
{
|
||||
def apply(beatBytes: Int, params: TLManagerParameters)(implicit valName: ValName) =
|
||||
new TLManagerNode(Seq(TLManagerPortParameters(Seq(params), beatBytes, minLatency = 0)))
|
||||
}
|
||||
|
||||
case class TLAdapterNode(
|
||||
clientFn: TLClientPortParameters => TLClientPortParameters,
|
||||
managerFn: TLManagerPortParameters => TLManagerPortParameters,
|
||||
clientFn: TLClientPortParameters => TLClientPortParameters = { s => s },
|
||||
managerFn: TLManagerPortParameters => TLManagerPortParameters = { s => s },
|
||||
num: Range.Inclusive = 0 to 999)(
|
||||
implicit valName: ValName)
|
||||
extends AdapterNode(TLImp)(clientFn, managerFn, num)
|
||||
|
||||
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)()
|
||||
|
||||
case class TLNexusNode(
|
||||
clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
|
||||
managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
|
||||
@ -101,43 +89,12 @@ abstract class TLCustomNode(
|
||||
implicit valName: ValName)
|
||||
extends CustomNode(TLImp)(numClientPorts, numManagerPorts)
|
||||
|
||||
// Nodes passed from an inner module
|
||||
case class TLOutputNode()(implicit valName: ValName) extends OutputNode(TLImp)
|
||||
case class TLInputNode()(implicit valName: ValName) extends InputNode(TLImp)
|
||||
|
||||
// Nodes used for external ports
|
||||
case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends BlindOutputNode(TLImp)(portParams)
|
||||
case class TLBlindInputNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends BlindInputNode(TLImp)(portParams)
|
||||
|
||||
case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends InternalOutputNode(TLImp)(portParams)
|
||||
case class TLInternalInputNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends InternalInputNode(TLImp)(portParams)
|
||||
|
||||
/** Synthesizeable unit tests */
|
||||
import freechips.rocketchip.unittest._
|
||||
|
||||
class TLInputNodeTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
|
||||
class Acceptor extends LazyModule {
|
||||
val node = TLInputNode()
|
||||
val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
|
||||
tlram.node := node
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
val fuzzer = LazyModule(new TLFuzzer(txns))
|
||||
LazyModule(new Acceptor).node := TLFragmenter(4, 64)(fuzzer.node)
|
||||
|
||||
io.finished := Module(fuzzer.module).io.finished
|
||||
}
|
||||
// Asynchronous crossings
|
||||
|
||||
object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncEdgeParameters, TLAsyncBundle]
|
||||
{
|
||||
def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
|
||||
def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
|
||||
def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p)
|
||||
def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p)
|
||||
|
||||
def bundleO(eo: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(eo.bundle)
|
||||
def bundleI(ei: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(ei.bundle)
|
||||
@ -152,9 +109,14 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor
|
||||
pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
|
||||
}
|
||||
|
||||
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)
|
||||
case class TLAsyncOutputNode()(implicit valName: ValName) extends OutputNode(TLAsyncImp)
|
||||
case class TLAsyncInputNode()(implicit valName: ValName) extends InputNode(TLAsyncImp)
|
||||
case class TLAsyncAdapterNode(
|
||||
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
|
||||
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s },
|
||||
num: Range.Inclusive = 0 to 999)(
|
||||
implicit valName: ValName)
|
||||
extends AdapterNode(TLAsyncImp)(clientFn, managerFn, num)
|
||||
|
||||
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)()
|
||||
|
||||
case class TLAsyncSourceNode(sync: Int)(implicit valName: ValName)
|
||||
extends MixedAdapterNode(TLImp, TLAsyncImp)(
|
||||
@ -166,10 +128,12 @@ case class TLAsyncSinkNode(depth: Int, sync: Int)(implicit valName: ValName)
|
||||
dFn = { p => p.base.copy(minLatency = sync+1) },
|
||||
uFn = { p => TLAsyncManagerPortParameters(depth, p) })
|
||||
|
||||
// Rationally related crossings
|
||||
|
||||
object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalEdgeParameters, TLRationalBundle]
|
||||
{
|
||||
def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu)
|
||||
def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu)
|
||||
def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p)
|
||||
def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p)
|
||||
|
||||
def bundleO(eo: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(eo.bundle)
|
||||
def bundleI(ei: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(ei.bundle)
|
||||
@ -182,9 +146,14 @@ object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalM
|
||||
pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
|
||||
}
|
||||
|
||||
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)
|
||||
case class TLRationalOutputNode()(implicit valName: ValName) extends OutputNode(TLRationalImp)
|
||||
case class TLRationalInputNode()(implicit valName: ValName) extends InputNode(TLRationalImp)
|
||||
case class TLRationalAdapterNode(
|
||||
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
|
||||
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s },
|
||||
num: Range.Inclusive = 0 to 999)(
|
||||
implicit valName: ValName)
|
||||
extends AdapterNode(TLRationalImp)(clientFn, managerFn, num)
|
||||
|
||||
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)()
|
||||
|
||||
case class TLRationalSourceNode()(implicit valName: ValName)
|
||||
extends MixedAdapterNode(TLImp, TLRationalImp)(
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util.RationalDirection
|
||||
import scala.math.max
|
||||
@ -312,7 +313,8 @@ object TLBundleParameters
|
||||
|
||||
case class TLEdgeParameters(
|
||||
client: TLClientPortParameters,
|
||||
manager: TLManagerPortParameters)
|
||||
manager: TLManagerPortParameters,
|
||||
params: Parameters)
|
||||
{
|
||||
val maxTransfer = max(client.maxTransfer, manager.maxTransfer)
|
||||
val maxLgSize = log2Ceil(maxTransfer)
|
||||
@ -340,7 +342,7 @@ object TLAsyncBundleParameters
|
||||
def union(x: Seq[TLAsyncBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
|
||||
}
|
||||
|
||||
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters)
|
||||
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters)
|
||||
{
|
||||
val bundle = TLAsyncBundleParameters(manager.depth, TLBundleParameters(client.base, manager.base))
|
||||
}
|
||||
@ -348,7 +350,7 @@ case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: T
|
||||
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLManagerPortParameters)
|
||||
case class TLRationalClientPortParameters(base: TLClientPortParameters)
|
||||
|
||||
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters)
|
||||
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters)
|
||||
{
|
||||
val bundle = TLBundleParameters(client.base, manager.base)
|
||||
}
|
||||
|
||||
@ -38,13 +38,12 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter
|
||||
val node = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(name = name)))))
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val tl_out = node.bundleOut
|
||||
val io = IO(new Bundle {
|
||||
val run = Bool(INPUT)
|
||||
val done = Bool(OUTPUT)
|
||||
}
|
||||
})
|
||||
|
||||
val edgeOut = node.edgesOut(0)
|
||||
val (tl_out, edgeOut) = node.out(0)
|
||||
pattern.foreach { p =>
|
||||
require (p.size <= log2Ceil(edgeOut.manager.beatBytes), "Patterns must fit in a single beat")
|
||||
}
|
||||
@ -56,8 +55,8 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter
|
||||
val end = step === UInt(pattern.size)
|
||||
io.done := end && !flight
|
||||
|
||||
val a = io.tl_out(0).a
|
||||
val d = io.tl_out(0).d
|
||||
val a = tl_out.a
|
||||
val d = tl_out.d
|
||||
|
||||
// Expected response?
|
||||
val check = Vec(pattern.map(p => Bool(p.dataIn.isDefined)))(step) holdUnless a.fire()
|
||||
@ -80,8 +79,8 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter
|
||||
d.ready := Bool(true)
|
||||
|
||||
// Tie off unused channels
|
||||
io.tl_out(0).b.ready := Bool(true)
|
||||
io.tl_out(0).c.valid := Bool(false)
|
||||
io.tl_out(0).e.valid := Bool(false)
|
||||
tl_out.b.ready := Bool(true)
|
||||
tl_out.c.valid := Bool(false)
|
||||
tl_out.e.valid := Bool(false)
|
||||
}
|
||||
}
|
||||
|
||||
@ -24,15 +24,10 @@ import freechips.rocketchip.util._
|
||||
|
||||
class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLIdentityNode()
|
||||
val node = TLAdapterNode()
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
val edge = edgeIn
|
||||
val endAddress = edge.manager.maxAddress + 1
|
||||
val endSourceId = edge.client.endSourceId
|
||||
|
||||
@ -20,12 +20,7 @@ class TLRationalCrossingSource(implicit p: Parameters) extends LazyModule
|
||||
val node = TLRationalSourceNode()
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
|
||||
val direction = edgeOut.manager.direction
|
||||
|
||||
@ -56,12 +51,7 @@ class TLRationalCrossingSink(direction: RationalDirection = Symmetric)(implicit
|
||||
val node = TLRationalSinkNode(direction)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe
|
||||
val direction = edgeIn.manager.direction
|
||||
|
||||
@ -109,8 +99,8 @@ object TLRationalCrossingSink
|
||||
|
||||
class TLRationalCrossing(direction: RationalDirection = Symmetric)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val nodeIn = TLInputNode()
|
||||
val nodeOut = TLOutputNode()
|
||||
val nodeIn = TLIdentityNode()
|
||||
val nodeOut = TLIdentityNode()
|
||||
val node = NodeHandle(nodeIn, nodeOut)
|
||||
|
||||
val source = LazyModule(new TLRationalCrossingSource)
|
||||
@ -121,14 +111,12 @@ class TLRationalCrossing(direction: RationalDirection = Symmetric)(implicit p: P
|
||||
val out = (nodeOut := sink.node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = nodeIn.bundleIn
|
||||
val io = IO(new Bundle {
|
||||
val in_clock = Clock(INPUT)
|
||||
val in_reset = Bool(INPUT)
|
||||
val out = nodeOut.bundleOut
|
||||
val out_clock = Clock(INPUT)
|
||||
val out_reset = Bool(INPUT)
|
||||
}
|
||||
})
|
||||
|
||||
source.module.clock := io.in_clock
|
||||
source.module.reset := io.in_reset
|
||||
@ -150,7 +138,7 @@ class TLRationalCrossing(direction: RationalDirection = Symmetric)(implicit p: P
|
||||
import freechips.rocketchip.unittest._
|
||||
|
||||
class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val node = TLRationalOutputNode()
|
||||
val node = TLRationalIdentityNode()
|
||||
val fuzz = LazyModule(new TLFuzzer(txns))
|
||||
val model = LazyModule(new TLRAMModel(name))
|
||||
|
||||
@ -158,25 +146,20 @@ class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameter
|
||||
node := TLRationalCrossingSource()(TLDelayer(0.25)(model.node))
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val io = IO(new Bundle {
|
||||
val finished = Bool(OUTPUT)
|
||||
val out = node.bundleOut
|
||||
}
|
||||
})
|
||||
io.finished := fuzz.module.io.finished
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parameters) extends LazyModule {
|
||||
val node = TLRationalInputNode()
|
||||
val node = TLRationalIdentityNode()
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
|
||||
ram.node := TLFragmenter(4, 256)(TLDelayer(0.25)(TLRationalCrossingSink(direction)(node)))
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
}
|
||||
}
|
||||
lazy val module = new LazyModuleImp(this) { }
|
||||
}
|
||||
|
||||
class TLRAMRationalCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
|
||||
@ -196,7 +179,7 @@ class TLRAMRationalCrossing(txns: Int)(implicit p: Parameters) extends LazyModul
|
||||
val fix_fast_sink = LazyModule(new TLRAMRationalCrossingSink(SlowToFast))
|
||||
fix_fast_sink.node := fix_slow_source.node
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished :=
|
||||
sym_fast_source.module.io.finished &&
|
||||
sym_slow_source.module.io.finished &&
|
||||
|
||||
@ -40,9 +40,9 @@ case class TLRegisterNode(
|
||||
// Calling this method causes the matching TL2 bundle to be
|
||||
// configured to route all requests to the listed RegFields.
|
||||
def regmap(mapping: RegField.Map*) = {
|
||||
val a = bundleIn(0).a
|
||||
val d = bundleIn(0).d
|
||||
val edge = edgesIn(0)
|
||||
val (bundleIn, edge) = this.in(0)
|
||||
val a = bundleIn.a
|
||||
val d = bundleIn.d
|
||||
|
||||
// Please forgive me ...
|
||||
val baseEnd = 0
|
||||
@ -76,9 +76,9 @@ case class TLRegisterNode(
|
||||
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
|
||||
|
||||
// Tie off unused channels
|
||||
bundleIn(0).b.valid := Bool(false)
|
||||
bundleIn(0).c.ready := Bool(true)
|
||||
bundleIn(0).e.ready := Bool(true)
|
||||
bundleIn.b.valid := Bool(false)
|
||||
bundleIn.c.ready := Bool(true)
|
||||
bundleIn.e.ready := Bool(true)
|
||||
}
|
||||
}
|
||||
|
||||
@ -92,13 +92,11 @@ abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val
|
||||
val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int"))))
|
||||
}
|
||||
|
||||
case class TLRegBundleArg(interrupts: HeterogeneousBag[Vec[Bool]], in: HeterogeneousBag[TLBundle])(implicit val p: Parameters)
|
||||
case class TLRegBundleArg()(implicit val p: Parameters)
|
||||
|
||||
class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
|
||||
{
|
||||
implicit val p = arg.p
|
||||
val interrupts = arg.interrupts
|
||||
val in = arg.in
|
||||
}
|
||||
|
||||
class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters) extends TLRegBundleBase(arg)
|
||||
@ -106,8 +104,8 @@ class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters)
|
||||
class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
|
||||
extends LazyModuleImp(router) with HasRegMap
|
||||
{
|
||||
val io = bundleBuilder
|
||||
val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
|
||||
val io = IO(bundleBuilder)
|
||||
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1
|
||||
val address = router.address
|
||||
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
|
||||
}
|
||||
@ -129,5 +127,5 @@ class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp](
|
||||
require (isPow2(size))
|
||||
// require (size >= 4096) ... not absolutely required, but highly recommended
|
||||
|
||||
lazy val module = moduleBuilder(bundleBuilder(TLRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
|
||||
lazy val module = moduleBuilder(bundleBuilder(TLRegBundleArg()), this)
|
||||
}
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.experimental.MultiIOModule
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.regmapper._
|
||||
@ -222,7 +223,7 @@ trait RRTest1Bundle
|
||||
{
|
||||
}
|
||||
|
||||
trait RRTest1Module extends Module with HasRegMap
|
||||
trait RRTest1Module extends MultiIOModule with HasRegMap
|
||||
{
|
||||
val clocks = Module(new Pow2ClockDivider(2))
|
||||
|
||||
@ -261,7 +262,7 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
|
||||
|
||||
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
}
|
||||
}
|
||||
@ -276,7 +277,7 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
|
||||
|
||||
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
}
|
||||
}
|
||||
|
||||
@ -29,18 +29,12 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4,
|
||||
// We require the address range to include an entire beat (for the write mask)
|
||||
require ((address.mask & (beatBytes-1)) == beatBytes-1)
|
||||
|
||||
lazy val module = new Implementation
|
||||
@chiselName class Implementation extends LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
}
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
|
||||
if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
|
||||
val mask = bigBits(address.mask >> log2Ceil(beatBytes))
|
||||
|
||||
val in = io.in(0)
|
||||
val edge = node.edgesIn(0)
|
||||
val (in, edge) = node.in(0)
|
||||
|
||||
val addrBits = (mask zip edge.addr_hi(in.a.bits).toBools).filter(_._1).map(_._2)
|
||||
val a_legal = address.contains(in.a.bits.address)
|
||||
@ -101,7 +95,7 @@ class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends
|
||||
model.node := fuzz.node
|
||||
ram.node := TLDelayer(0.25)(model.node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
}
|
||||
}
|
||||
|
||||
@ -23,12 +23,7 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
|
||||
managerFn = { mp => mp.copy(managers = mp.managers.map(_.copy(fifoId = None))) })
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
// Acquires cannot pass this adapter; it makes Probes impossible
|
||||
require (!edgeIn.client.anySupportProbe ||
|
||||
!edgeOut.manager.anySupportAcquireB)
|
||||
|
||||
@ -15,9 +15,6 @@ case class TLSplitterNode(
|
||||
implicit valName: ValName)
|
||||
extends TLCustomNode(numClientPorts, numManagerPorts)
|
||||
{
|
||||
val externalIn = true
|
||||
val externalOut = true
|
||||
|
||||
def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
|
||||
require (oKnown == 0, s"${name} (a splitter) appears right of a := or :*=; use a :=* instead${lazyModule.line}")
|
||||
require (iStars == 0, s"${name} (a splitter) cannot appear left of a :*=; did you mean :=*?${lazyModule.line}")
|
||||
@ -65,18 +62,14 @@ class TLSplitter(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Pa
|
||||
})
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
def group[T](x: Seq[T]) =
|
||||
if (x.isEmpty) Nil else x.grouped(node.edgesIn.size).toList.transpose
|
||||
if (x.isEmpty) Nil else x.grouped(node.in.size).toList.transpose
|
||||
|
||||
if (node.edgesOut.size == node.edgesIn.size) {
|
||||
io.out <> io.in
|
||||
} else ((node.edgesIn zip io.in) zip (group(node.edgesOut) zip group(io.out))) foreach {
|
||||
case ((edgeIn, io_in), (edgesOut, io_out)) =>
|
||||
if (node.out.size == node.in.size) {
|
||||
(node.in zip node.out) foreach { case ((i, _), (o, _)) => o <> i }
|
||||
} else (node.in zip group(node.out)) foreach {
|
||||
case ((io_in, edgeIn), seq) =>
|
||||
val (io_out, edgesOut) = seq.unzip
|
||||
|
||||
// Grab the port ID mapping
|
||||
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
|
||||
|
||||
@ -53,12 +53,7 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
|
||||
val node = TLToAHBNode()
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
val beatBytes = edgeOut.slave.beatBytes
|
||||
val maxTransfer = edgeOut.slave.maxTransfer
|
||||
val lgMax = log2Ceil(maxTransfer)
|
||||
|
||||
@ -38,12 +38,7 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod
|
||||
val node = TLToAPBNode()
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
val beatBytes = edgeOut.slave.beatBytes
|
||||
val lgBytes = log2Ceil(beatBytes)
|
||||
|
||||
|
||||
@ -53,12 +53,7 @@ class TLToAXI4(val beatBytes: Int, val combinational: Boolean = true, val adapte
|
||||
val node = TLToAXI4Node(beatBytes, stripBits)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
val slaves = edgeOut.slave.slaves
|
||||
|
||||
// All pairs of slaves must promise that they will never interleave data
|
||||
|
||||
@ -17,11 +17,6 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
|
||||
managerFn = { case m => m.copy(beatBytes = innerBeatBytes) })
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
|
||||
val inBytes = edgeIn.manager.beatBytes
|
||||
val outBytes = edgeOut.manager.beatBytes
|
||||
@ -154,7 +149,7 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
|
||||
}
|
||||
}
|
||||
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
|
||||
|
||||
// If the master is narrower than the slave, the D channel must be narrowed.
|
||||
// This is tricky, because the D channel has no address data.
|
||||
@ -220,7 +215,7 @@ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameter
|
||||
TLWidthWidget(second)(
|
||||
TLWidthWidget(first)(TLDelayer(0.1)(model.node)))}))
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
}
|
||||
}
|
||||
|
||||
@ -63,22 +63,21 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
|
||||
})
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
if ((node.in.size * node.out.size) > (8*32)) {
|
||||
println (s"!!! WARNING !!!")
|
||||
println (s" Your TLXbar ($name) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
|
||||
println (s"!!! WARNING !!!")
|
||||
}
|
||||
|
||||
if ((io.in.size * io.out.size) > (8*32)) {
|
||||
println (s"!!! WARNING !!!")
|
||||
println (s" Your TLXbar ($name) is very large, with ${io.in.size} Masters and ${io.out.size} Slaves.")
|
||||
println (s"!!! WARNING !!!")
|
||||
}
|
||||
val (io_in, edgesIn) = node.in.unzip
|
||||
val (io_out, edgesOut) = node.out.unzip
|
||||
|
||||
// Grab the port ID mapping
|
||||
val inputIdRanges = TLXbar.mapInputIds(node.edgesIn.map(_.client))
|
||||
val outputIdRanges = TLXbar.mapOutputIds(node.edgesOut.map(_.manager))
|
||||
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
|
||||
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
|
||||
|
||||
// Find a good mask for address decoding
|
||||
val port_addrs = node.edgesOut.map(_.manager.managers.map(_.address).flatten)
|
||||
val port_addrs = edgesOut.map(_.manager.managers.map(_.address).flatten)
|
||||
val routingMask = AddressDecoder(port_addrs)
|
||||
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
|
||||
val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
|
||||
@ -97,70 +96,70 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
|
||||
// Print the ID mapping
|
||||
if (false) {
|
||||
println(s"XBar ${name} mapping:")
|
||||
(node.edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
|
||||
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
|
||||
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
|
||||
}
|
||||
println("")
|
||||
}
|
||||
|
||||
// We need an intermediate size of bundle with the widest possible identifiers
|
||||
val wide_bundle = TLBundleParameters.union(io.in.map(_.params) ++ io.out.map(_.params))
|
||||
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
|
||||
|
||||
// Handle size = 1 gracefully (Chisel3 empty range is broken)
|
||||
def trim(id: UInt, size: Int) = if (size <= 1) UInt(0) else id(log2Ceil(size)-1, 0)
|
||||
|
||||
// Transform input bundle sources (sinks use global namespace on both sides)
|
||||
val in = Wire(Vec(io.in.size, TLBundle(wide_bundle)))
|
||||
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
|
||||
for (i <- 0 until in.size) {
|
||||
val r = inputIdRanges(i)
|
||||
|
||||
in(i).a <> io.in(i).a
|
||||
io.in(i).d <> in(i).d
|
||||
in(i).a.bits.source := io.in(i).a.bits.source | UInt(r.start)
|
||||
io.in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
|
||||
in(i).a <> io_in(i).a
|
||||
io_in(i).d <> in(i).d
|
||||
in(i).a.bits.source := io_in(i).a.bits.source | UInt(r.start)
|
||||
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
|
||||
|
||||
if (node.edgesIn(i).client.anySupportProbe && node.edgesOut.exists(_.manager.anySupportAcquireB)) {
|
||||
in(i).c <> io.in(i).c
|
||||
in(i).e <> io.in(i).e
|
||||
io.in(i).b <> in(i).b
|
||||
in(i).c.bits.source := io.in(i).c.bits.source | UInt(r.start)
|
||||
io.in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
|
||||
if (edgesIn(i).client.anySupportProbe && edgesOut.exists(_.manager.anySupportAcquireB)) {
|
||||
in(i).c <> io_in(i).c
|
||||
in(i).e <> io_in(i).e
|
||||
io_in(i).b <> in(i).b
|
||||
in(i).c.bits.source := io_in(i).c.bits.source | UInt(r.start)
|
||||
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
|
||||
} else {
|
||||
in(i).c.valid := Bool(false)
|
||||
in(i).e.valid := Bool(false)
|
||||
in(i).b.ready := Bool(false)
|
||||
io.in(i).c.ready := Bool(true)
|
||||
io.in(i).e.ready := Bool(true)
|
||||
io.in(i).b.valid := Bool(false)
|
||||
io_in(i).c.ready := Bool(true)
|
||||
io_in(i).e.ready := Bool(true)
|
||||
io_in(i).b.valid := Bool(false)
|
||||
}
|
||||
}
|
||||
|
||||
// Transform output bundle sinks (sources use global namespace on both sides)
|
||||
val out = Wire(Vec(io.out.size, TLBundle(wide_bundle)))
|
||||
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
|
||||
for (i <- 0 until out.size) {
|
||||
val r = outputIdRanges(i)
|
||||
|
||||
io.out(i).a <> out(i).a
|
||||
out(i).d <> io.out(i).d
|
||||
out(i).d.bits.sink := io.out(i).d.bits.sink | UInt(r.map(_.start).getOrElse(0))
|
||||
io_out(i).a <> out(i).a
|
||||
out(i).d <> io_out(i).d
|
||||
out(i).d.bits.sink := io_out(i).d.bits.sink | UInt(r.map(_.start).getOrElse(0))
|
||||
|
||||
if (node.edgesOut(i).manager.anySupportAcquireB && node.edgesIn.exists(_.client.anySupportProbe)) {
|
||||
io.out(i).c <> out(i).c
|
||||
io.out(i).e <> out(i).e
|
||||
out(i).b <> io.out(i).b
|
||||
io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.map(_.size).getOrElse(0))
|
||||
if (edgesOut(i).manager.anySupportAcquireB && edgesIn.exists(_.client.anySupportProbe)) {
|
||||
io_out(i).c <> out(i).c
|
||||
io_out(i).e <> out(i).e
|
||||
out(i).b <> io_out(i).b
|
||||
io_out(i).e.bits.sink := trim(out(i).e.bits.sink, r.map(_.size).getOrElse(0))
|
||||
} else {
|
||||
out(i).c.ready := Bool(false)
|
||||
out(i).e.ready := Bool(false)
|
||||
out(i).b.valid := Bool(false)
|
||||
io.out(i).c.valid := Bool(false)
|
||||
io.out(i).e.valid := Bool(false)
|
||||
io.out(i).b.ready := Bool(true)
|
||||
io_out(i).c.valid := Bool(false)
|
||||
io_out(i).e.valid := Bool(false)
|
||||
io_out(i).b.ready := Bool(true)
|
||||
}
|
||||
}
|
||||
|
||||
val addressA = (in zip node.edgesIn) map { case (i, e) => e.address(i.a.bits) }
|
||||
val addressC = (in zip node.edgesIn) map { case (i, e) => e.address(i.c.bits) }
|
||||
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
|
||||
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
|
||||
|
||||
val requestAIO = Vec(addressA.map { i => Vec(outputPorts.map { o => o(i) }) })
|
||||
val requestCIO = Vec(addressC.map { i => Vec(outputPorts.map { o => o(i) }) })
|
||||
@ -168,28 +167,28 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
|
||||
val requestDOI = Vec(out.map { o => Vec(inputIdRanges.map { i => i.contains(o.d.bits.source) }) })
|
||||
val requestEIO = Vec(in.map { i => Vec(outputIdRanges.map { o => o.map(_.contains(i.e.bits.sink)).getOrElse(Bool(false)) }) })
|
||||
|
||||
val beatsAI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) })
|
||||
val beatsBO = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) })
|
||||
val beatsCI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) })
|
||||
val beatsDO = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) })
|
||||
val beatsEI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) })
|
||||
val beatsAI = Vec((in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) })
|
||||
val beatsBO = Vec((out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) })
|
||||
val beatsCI = Vec((in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) })
|
||||
val beatsDO = Vec((out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) })
|
||||
val beatsEI = Vec((in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) })
|
||||
|
||||
// Which pairs support support transfers
|
||||
def transpose[T](x: Seq[Seq[T]]) = Seq.tabulate(x(0).size) { i => Seq.tabulate(x.size) { j => x(j)(i) } }
|
||||
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
|
||||
|
||||
// Fanout the input sources to the output sinks
|
||||
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, node.paramsOut.map(_(ForceFanoutKey).a)) })
|
||||
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, node.paramsIn .map(_(ForceFanoutKey).b)) })
|
||||
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, node.paramsOut.map(_(ForceFanoutKey).c)) })
|
||||
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, node.paramsIn .map(_(ForceFanoutKey).d)) })
|
||||
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, node.paramsOut.map(_(ForceFanoutKey).e)) })
|
||||
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
|
||||
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
|
||||
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
|
||||
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
|
||||
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
|
||||
|
||||
// Arbitrate amongst the sources
|
||||
for (o <- 0 until out.size) {
|
||||
val allowI = Seq.tabulate(in.size) { i =>
|
||||
node.edgesIn(i).client.anySupportProbe &&
|
||||
node.edgesOut(o).manager.anySupportAcquireB
|
||||
edgesIn(i).client.anySupportProbe &&
|
||||
edgesOut(o).manager.anySupportAcquireB
|
||||
}
|
||||
TLArbiter(policy)(out(o).a, (beatsAI zip portsAOI(o) ):_*)
|
||||
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), allowI):_*)
|
||||
@ -198,8 +197,8 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
|
||||
|
||||
for (i <- 0 until in.size) {
|
||||
val allowO = Seq.tabulate(out.size) { o =>
|
||||
node.edgesIn(i).client.anySupportProbe &&
|
||||
node.edgesOut(o).manager.anySupportAcquireB
|
||||
edgesIn(i).client.anySupportProbe &&
|
||||
edgesOut(o).manager.anySupportAcquireB
|
||||
}
|
||||
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), allowO):_*)
|
||||
TLArbiter(policy)(in(i).d, (beatsDO zip portsDIO(i) ):_*)
|
||||
@ -264,7 +263,7 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM
|
||||
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
|
||||
}
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
}
|
||||
}
|
||||
@ -287,7 +286,7 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa
|
||||
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
|
||||
}
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzzers.last.module.io.finished
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user