riscv/rocket-chip
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diplomacy: change API to auto-create node bundles => cross-module refs

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This commit is contained in:
Wesley W. Terpstra
2017-09-13 18:06:03 -07:00
parent 53f6999ea8
commit 9217baf9d4
86 changed files with 575 additions and 933 deletions
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5
src/main/scala/tile/BaseTile.scala
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@@ -66,21 +66,20 @@ abstract class BareTileBundle[+L <: BareTile](_outer: L) extends GenericParamete
abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
val outer = _outer
val io = _io ()
val io = IO(_io ())
}
/** Uses TileLink master port to connect caches and accelerators to the coreplex */
trait HasTileLinkMasterPort {
implicit val p: Parameters
val module: HasTileLinkMasterPortModule
val masterNode = TLOutputNode()
val masterNode = TLIdentityNode()
val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
masterNode := tileBus.node
}
trait HasTileLinkMasterPortBundle {
val outer: HasTileLinkMasterPort
val master = outer.masterNode.bundleOut
}
trait HasTileLinkMasterPortModule {

3
src/main/scala/tile/Interrupts.scala
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@@ -38,7 +38,6 @@ trait HasExternalInterrupts extends HasTileParameters {
trait HasExternalInterruptsBundle {
val outer: HasExternalInterrupts
val interrupts = outer.intNode.bundleIn
}
trait HasExternalInterruptsModule {
@@ -57,6 +56,6 @@ trait HasExternalInterruptsModule {
val core_ips = core.lip
(async_ips ++ periph_ips ++ seip ++ core_ips).zip(io.interrupts(0)).foreach { case(c, i) => c := i }
(async_ips ++ periph_ips ++ seip ++ core_ips).zip(outer.intNode.in(0)._1).foreach { case(c, i) => c := i }
}
}

14
src/main/scala/tile/LazyRoCC.scala
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@@ -60,13 +60,11 @@ class RoCCCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
abstract class LazyRoCC(implicit p: Parameters) extends LazyModule {
val module: LazyRoCCModule
val atlNode: TLMixedNode = TLOutputNode()
val tlNode: TLMixedNode = TLOutputNode()
val atlNode: TLMixedNode = TLIdentityNode()
val tlNode: TLMixedNode = TLIdentityNode()
}
class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {
val atl = outer.atlNode.bundleOut
val tl = outer.tlNode.bundleOut
// Should be handled differently, eventually
val ptw = Vec(p(RoccNPTWPorts), new TLBPTWIO)
val fpu_req = Decoupled(new FPInput)
@@ -74,7 +72,7 @@ class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {
}
class LazyRoCCModule(outer: LazyRoCC) extends LazyModuleImp(outer) {
val io = new RoCCIO(outer)
val io = IO(new RoCCIO(outer))
}
/** Mixins for including RoCC **/
@@ -263,7 +261,7 @@ class TranslatorExampleModule(outer: TranslatorExample)(implicit p: Parameters)
class CharacterCountExample(implicit p: Parameters) extends LazyRoCC {
override lazy val module = new CharacterCountExampleModule(this)
override val atlNode = TLClientNode(TLClientParameters("CharacterCountRoCC"))
override val atlNode = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters("CharacterCountRoCC")))))
}
class CharacterCountExampleModule(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModule(outer)
@@ -286,7 +284,7 @@ class CharacterCountExampleModule(outer: CharacterCountExample)(implicit p: Para
val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(Bits(), 5)
val state = Reg(init = s_idle)
val tl_out = io.atl.head
val (tl_out, edgesOut) = outer.atlNode.out(0)
val gnt = tl_out.d.bits
val recv_data = Reg(UInt(width = cacheDataBits))
val recv_beat = Reg(UInt(width = log2Up(cacheDataBeats+1)), init = UInt(0))
@@ -309,7 +307,7 @@ class CharacterCountExampleModule(outer: CharacterCountExample)(implicit p: Para
io.resp.bits.rd := resp_rd
io.resp.bits.data := count
tl_out.a.valid := (state === s_acq)
tl_out.a.bits := outer.atlNode.edgesOut(0).Get(
tl_out.a.bits := edgesOut.Get(
fromSource = UInt(0),
toAddress = addr_block << blockOffset,
lgSize = UInt(lgCacheBlockBytes))._2

38
src/main/scala/tile/RocketTile.scala
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@@ -82,7 +82,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
}))
// Find all the caches
val outer = masterNode.edgesOut
val outer = masterNode.out.map(_._2)
.flatMap(_.manager.managers)
.filter(_.supportsAcquireB)
.flatMap(_.resources.headOption)
@@ -115,7 +115,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartid)))
Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartid)))
intNode.edgesIn.flatMap(_.source.sources).map { case s =>
intNode.in.flatMap(_._2.source.sources).map { case s =>
for (i <- s.range.start until s.range.end) {
csrIntMap.lift(i).foreach { j =>
s.resources.foreach { r =>
@@ -181,12 +181,12 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
val rocket = LazyModule(new RocketTile(rtp, hartid))
val masterNode: OutputNode[_,_,_,_,_]
val slaveNode: InputNode[_,_,_,_,_]
val intOutputNode = rocket.intOutputNode.map(dummy => IntOutputNode())
val asyncIntNode = IntInputNode()
val periphIntNode = IntInputNode()
val coreIntNode = IntInputNode()
val masterNode: IdentityNode[_,_,_,_,_]
val slaveNode: IdentityNode[_,_,_,_,_]
val asyncIntNode = IntIdentityNode()
val periphIntNode = IntIdentityNode()
val coreIntNode = IntIdentityNode()
val intOutputNode = rocket.intOutputNode.map(dummy => IntIdentityNode())
val intXbar = LazyModule(new IntXbar)
rocket.intNode := intXbar.intnode
@@ -220,18 +220,12 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
}
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle
val io = IO(new CoreBundle
with HasExternallyDrivenTileConstants
with CanHaveInstructionTracePort
with CanHaltAndCatchFire {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val outputInterrupts = intOutputNode.map(_.bundleOut)
val asyncInterrupts = asyncIntNode.bundleIn
val periphInterrupts = periphIntNode.bundleIn
val coreInterrupts = coreIntNode.bundleIn
val halt_and_catch_fire = rocket.module.io.halt_and_catch_fire.map(_.cloneType)
}
})
// signals that do not change based on crossing type:
rocket.module.io.hartid := io.hartid
rocket.module.io.reset_vector := io.reset_vector
@@ -241,10 +235,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
}
class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLOutputNode()
val masterNode = TLIdentityNode()
masterNode :=* optionalMasterBuffer(rocket.masterNode)
val slaveNode = new TLInputNode()(ValName("slave")) { override def reverse = true }
val slaveNode = new TLIdentityNode() { override def reverse = true }
DisableMonitors { implicit p => rocket.slaveNode :*= optionalSlaveBuffer(slaveNode) }
// Fully async interrupts need synchronizers.
@@ -260,12 +254,12 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
}
class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLAsyncOutputNode()
val masterNode = TLAsyncIdentityNode()
val source = LazyModule(new TLAsyncCrossingSource)
source.node :=* rocket.masterNode
masterNode :=* source.node
val slaveNode = new TLAsyncInputNode()(ValName("slave")) { override def reverse = true }
val slaveNode = new TLAsyncIdentityNode() { override def reverse = true }
val sink = LazyModule(new TLAsyncCrossingSink)
DisableMonitors { implicit p =>
@@ -289,12 +283,12 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
}
class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLRationalOutputNode()
val masterNode = TLRationalIdentityNode()
val source = LazyModule(new TLRationalCrossingSource)
source.node :=* optionalMasterBuffer(rocket.masterNode)
masterNode :=* source.node
val slaveNode = new TLRationalInputNode()(ValName("slave")) { override def reverse = true }
val slaveNode = new TLRationalIdentityNode() { override def reverse = true }
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
DisableMonitors { implicit p =>