riscv/rocket-chip
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diplomacy: change API to auto-create node bundles => cross-module refs

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This commit is contained in:
Wesley W. Terpstra
2017-09-13 18:06:03 -07:00
parent 53f6999ea8
commit 9217baf9d4
86 changed files with 575 additions and 933 deletions
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9
src/main/scala/rocket/BusErrorUnit.scala
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@ -37,11 +37,9 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
beatBytes = p(XLen)/8)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val tl = node.bundleIn
val interrupt = intNode.bundleOut
val io = IO(new Bundle {
val errors = t.flip
}
})
val sources = io.errors.toErrorList
val mask = sources.map(_.nonEmpty.B).asUInt
@ -61,7 +59,8 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
}
}
io.interrupt.head(0) := (accrued & interrupt).orR
val (int_out, _) = intNode.out(0)
int_out(0) := (accrued & interrupt).orR
def reg(r: UInt) = RegField(regWidth, r)
def maskedReg(r: UInt, m: UInt) = RegField(regWidth, r, RegWriteFn((v, d) => { when (v) { r := d & m }; true }))

10
src/main/scala/rocket/Frontend.scala
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@ -56,8 +56,8 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new FrontendModule(this)
val icache = LazyModule(new ICache(icacheParams, hartid))
val masterNode = TLOutputNode()
val slaveNode = TLInputNode()
val masterNode = TLIdentityNode()
val slaveNode = TLIdentityNode()
masterNode := icache.masterNode
// Avoid breaking tile dedup due to address constants in the monitor
@ -68,16 +68,14 @@ class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p)
with HasExternallyDrivenTileConstants {
val cpu = new FrontendIO().flip
val ptw = new TLBPTWIO()
val tl_out = outer.masterNode.bundleOut
val tl_in = outer.slaveNode.bundleIn
val errors = new ICacheErrors
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
with HasCoreParameters
with HasL1ICacheParameters {
val io = new FrontendBundle(outer)
implicit val edge = outer.masterNode.edgesOut.head
val io = IO(new FrontendBundle(outer))
implicit val edge = outer.masterNode.out(0)._2
val icache = outer.icache.module
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)

7
src/main/scala/rocket/HellaCache.scala
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@ -176,15 +176,14 @@ class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends CoreBu
val hartid = UInt(INPUT, hartIdLen)
val cpu = (new HellaCacheIO).flip
val ptw = new TLBPTWIO()
val mem = outer.node.bundleOut
val errors = new DCacheErrors
}
class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters {
implicit val edge = outer.node.edgesOut(0)
val io = new HellaCacheBundle(outer)
val tl_out = io.mem(0)
implicit val edge = outer.node.out(0)._2
val tl_out = outer.node.out(0)._1
val io = IO(new HellaCacheBundle(outer))
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable)
fifoManagers.foreach { m =>

15
src/main/scala/rocket/ICache.scala
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@ -45,9 +45,9 @@ class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new ICacheModule(this)
val masterNode = TLClientNode(TLClientParameters(
val masterNode = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(
sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint
name = s"Core ${hartid} ICache"))
name = s"Core ${hartid} ICache")))))
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
val device = new SimpleDevice("itim", Seq("sifive,itim0"))
@ -91,8 +91,6 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
val resp = Valid(new ICacheResp(outer))
val invalidate = Bool(INPUT)
val tl_out = outer.masterNode.bundleOut
val tl_in = outer.slaveNode.map(_.bundleIn)
val errors = new ICacheErrors
val perf = new ICachePerfEvents().asOutput
@ -109,11 +107,10 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
with HasL1ICacheParameters {
override val cacheParams = outer.icacheParams // Use the local parameters
val io = new ICacheBundle(outer)
val edge_out = outer.masterNode.edgesOut.head
val tl_out = io.tl_out.head
val edge_in = outer.slaveNode.map(_.edgesIn.head)
val tl_in = io.tl_in.map(_.head)
val io = IO(new ICacheBundle(outer))
val (tl_out, edge_out) = outer.masterNode.out(0)
val tl_in = outer.slaveNode.map(_.in(0)._1)
val edge_in = outer.slaveNode.map(_.in(0)._2)
val tECC = cacheParams.tagECC
val dECC = cacheParams.dataECC

2
src/main/scala/rocket/PTW.scala
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@ -283,7 +283,7 @@ trait CanHavePTW extends HasHellaCache {
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edgesOut(0), outer.p))
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.out(0)._2, outer.p))
if (outer.usingPTW)
dcachePorts += ptw.io.mem
}

16
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -30,13 +30,11 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics:
minLatency = 1)))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val tl_in = node.bundleIn
val io = IO(new Bundle {
val dmem = new HellaCacheIO
}
})
val tl_in = io.tl_in(0)
val edge = node.edgesIn(0)
val (tl_in, edge) = node.in(0)
val s_ready :: s_wait :: s_replay :: s_grant :: Nil = Enum(UInt(), 4)
val state = Reg(init = s_ready)
@ -104,7 +102,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics)))
}
val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntOutputNode())
val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntIdentityNode())
val busErrorUnit = tileParams.core.tileControlAddr map { a =>
val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
intOutputNode.get := beu.intNode
@ -112,7 +110,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
}
// connect any combination of ITIM, DTIM, and BusErrorUnit
val slaveNode = TLInputNode()
val slaveNode = TLIdentityNode()
DisableMonitors { implicit p =>
val xbarPorts =
scratch.map(lm => (lm.node, xBytes)) ++
@ -129,7 +127,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
}
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
val finalNode = frontend.masterNode.edgesOut.head.manager.managers.find(_.nodePath.last == s.node)
val finalNode = frontend.masterNode.out.head._2.manager.managers.find(_.nodePath.last == s.node)
require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
finalNode.get.address(0)
@ -140,8 +138,6 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
trait CanHaveScratchpadBundle extends HasHellaCacheBundle with HasICacheFrontendBundle {
val outer: CanHaveScratchpad
val slave = outer.slaveNode.bundleIn
val intOutput = outer.intOutputNode.map(_.bundleOut)
}
trait CanHaveScratchpadModule extends HasHellaCacheModule with HasICacheFrontendModule {