diplomacy: change API to auto-create node bundles => cross-module refs
This commit is contained in:
Wesley W. Terpstra
@ -6,6 +6,7 @@ import Chisel._
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import chisel3.experimental.{BaseModule, RawModule, MultiIOModule, withClockAndReset}
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import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
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import freechips.rocketchip.config.Parameters
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import scala.collection.immutable.ListMap
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abstract class LazyModule()(implicit val p: Parameters)
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{
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@ -54,15 +55,6 @@ abstract class LazyModule()(implicit val p: Parameters)
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def module: LazyModuleImpLike
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protected[diplomacy] def instantiate() = {
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children.reverse.foreach { c =>
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// !!! fix chisel3 so we can pass the desired sourceInfo
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// implicit val sourceInfo = c.module.outer.info
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Module(c.module)
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}
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bindings.reverse.foreach { f => f () }
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}
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def omitGraphML: Boolean = !nodes.exists(!_.omitGraphML) && !children.exists(!_.omitGraphML)
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lazy val graphML: String = parent.map(_.graphML).getOrElse {
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val buf = new StringBuilder
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@ -144,6 +136,8 @@ object LazyModule
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sealed trait LazyModuleImpLike extends BaseModule
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{
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val wrapper: LazyModule
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val auto: AutoBundle
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protected[diplomacy] val dangles: Seq[Dangle]
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// .module had better not be accessed while LazyModules are still being built!
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require (LazyModule.stack.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.stack.head.name}")
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@ -152,18 +146,47 @@ sealed trait LazyModuleImpLike extends BaseModule
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suggestName(wrapper.instanceName)
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implicit val p = wrapper.p
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protected[diplomacy] def instantiate() = {
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val childDangles = wrapper.children.reverse.flatMap { c =>
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implicit val sourceInfo = c.info
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Module(c.module).dangles
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}
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val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
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val (toConnect, toForward) = (nodeDangles ++ childDangles).groupBy(_.source).partition(_._2.size == 2)
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val forward = toForward.map(_._2(0)).toList
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toConnect.foreach { case (_, Seq(a, b)) =>
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require (a.flipped != b.flipped)
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if (a.flipped) { a.data <> b.data } else { b.data <> a.data }
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}
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val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }:_*))
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val dangles = (forward zip auto.elements) map { case (d, (_, io)) =>
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if (d.flipped) { d.data <> io } else { io <> d.data }
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d.copy(data = io, name = wrapper.valName.getOrElse("anon") + "_" + d.name)
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}
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wrapper.bindings.reverse.foreach { f => f () }
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(auto, dangles)
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}
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}
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abstract class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
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wrapper.instantiate()
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}
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abstract class LazyMultiIOModuleImp(val wrapper: LazyModule) extends MultiIOModule with LazyModuleImpLike {
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wrapper.instantiate()
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abstract class LazyModuleImp(val wrapper: LazyModule) extends MultiIOModule with LazyModuleImpLike {
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val (auto, dangles) = instantiate()
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}
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abstract class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
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withClockAndReset(Bool(false).asClock, Bool(true)) {
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wrapper.instantiate()
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val (auto, dangles) = withClockAndReset(Bool(false).asClock, Bool(true)) {
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instantiate()
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}
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}
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case class HalfEdge(serial: Int, index: Int)
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case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, data: Data)
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final class AutoBundle(elts: (String, Data, Boolean)*) extends Record {
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// !!! need to fix-up name collision better than appending _#
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val elements = ListMap(elts.zipWithIndex map { case ((field, elt, flip), i) =>
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(field + "_" + i) -> (if (flip) elt.cloneType.flip else elt.cloneType)
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}:_*)
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override def cloneType = (new AutoBundle(elts:_*)).asInstanceOf[this.type]
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}
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@ -34,7 +34,7 @@ private case object MonitorsEnabled extends Field[Boolean](true)
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// BI = Bundle type used when connecting to the inner side of the node
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trait InwardNodeImp[DI, UI, EI, BI <: Data]
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{
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def edgeI(pd: DI, pu: UI): EI
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def edgeI(pd: DI, pu: UI, p: Parameters): EI
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def bundleI(ei: EI): BI
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def colour: String
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def reverse: Boolean = false
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@ -55,7 +55,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data]
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// BO = Bundle type used when connecting to the outer side of the node
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trait OutwardNodeImp[DO, UO, EO, BO <: Data]
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{
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def edgeO(pd: DO, pu: UO): EO
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def edgeO(pd: DO, pu: UO, p: Parameters): EO
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def bundleO(eo: EO): BO
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// optional methods to track node graph
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@ -75,11 +75,11 @@ abstract class BaseNode(implicit val valName: ValName)
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val index = lazyModule.nodes.size
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lazyModule.nodes = this :: lazyModule.nodes
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val externalIn: Boolean
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val externalOut: Boolean
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val serial = BaseNode.serial
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BaseNode.serial = BaseNode.serial + 1
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protected[diplomacy] def instantiate(): Seq[Dangle]
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def nodename = getClass.getName.split('.').last
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def name = lazyModule.name + "." + nodename
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def name = lazyModule.name + "." + valName.name
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def omitGraphML = outputs.isEmpty && inputs.isEmpty
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lazy val nodedebugstring: String = ""
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@ -91,6 +91,11 @@ abstract class BaseNode(implicit val valName: ValName)
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protected[diplomacy] def reverse: Boolean
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}
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object BaseNode
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{
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protected[diplomacy] var serial = 0
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}
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case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data]
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(inward: InwardNode[DI, UI, BI], outward: OutwardNode[DO, UO, BO])
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extends Object with InwardNodeHandle[DI, UI, BI] with OutwardNodeHandle[DO, UO, BO]
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@ -138,7 +143,6 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI,
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protected[diplomacy] val iStar: Int
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protected[diplomacy] val iPortMapping: Seq[(Int, Int)]
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protected[diplomacy] val iParams: Seq[UI]
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protected[diplomacy] val bundleIn: HeterogeneousBag[BI]
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}
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trait OutwardNodeHandle[DO, UO, BO <: Data]
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@ -171,10 +175,9 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO
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protected[diplomacy] val oStar: Int
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protected[diplomacy] val oPortMapping: Seq[(Int, Int)]
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protected[diplomacy] val oParams: Seq[DO]
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protected[diplomacy] val bundleOut: HeterogeneousBag[BO]
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}
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abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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protected[diplomacy] val numPO: Range.Inclusive,
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@ -213,22 +216,22 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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(oSum.init zip oSum.tail, iSum.init zip iSum.tail, oStar, iStar)
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}
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lazy val oPorts = oBindings.flatMap { case (i, n, _, _) =>
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lazy val oPorts = oBindings.flatMap { case (i, n, _, p) =>
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val (start, end) = n.iPortMapping(i)
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(start until end) map { j => (j, n) }
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(start until end) map { j => (j, n, p) }
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}
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lazy val iPorts = iBindings.flatMap { case (i, n, _, _) =>
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lazy val iPorts = iBindings.flatMap { case (i, n, _, p) =>
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val (start, end) = n.oPortMapping(i)
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(start until end) map { j => (j, n) }
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(start until end) map { j => (j, n, p) }
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}
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protected[diplomacy] lazy val oParams: Seq[DO] = {
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val o = mapParamsD(oPorts.size, iPorts.map { case (i, n) => n.oParams(i) })
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val o = mapParamsD(oPorts.size, iPorts.map { case (i, n, _) => n.oParams(i) })
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require (o.size == oPorts.size, s"Bug in diplomacy; ${name} has ${o.size} != ${oPorts.size} down/up outer parameters${lazyModule.line}")
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o.map(outer.mixO(_, this))
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}
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protected[diplomacy] lazy val iParams: Seq[UI] = {
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val i = mapParamsU(iPorts.size, oPorts.map { case (o, n) => n.iParams(o) })
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val i = mapParamsU(iPorts.size, oPorts.map { case (o, n, _) => n.iParams(o) })
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require (i.size == iPorts.size, s"Bug in diplomacy; ${name} has ${i.size} != ${iPorts.size} up/down inner parameters${lazyModule.line}")
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i.map(inner.mixI(_, this))
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}
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@ -236,23 +239,48 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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protected[diplomacy] def gco = if (iParams.size != 1) None else inner.getO(iParams(0))
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protected[diplomacy] def gci = if (oParams.size != 1) None else outer.getI(oParams(0))
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lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => outer.edgeO(o, n.iParams(i)) }
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lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => inner.edgeI(n.oParams(o), i) }
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lazy val externalEdgesOut = if (externalOut) {edgesOut} else { Seq() }
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lazy val externalEdgesIn = if (externalIn) {edgesIn} else { Seq() }
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protected[diplomacy] lazy val edgesOut = (oPorts zip oParams).map { case ((i, n, p), o) => outer.edgeO(o, n.iParams(i), p) }
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protected[diplomacy] lazy val edgesIn = (iPorts zip iParams).map { case ((o, n, p), i) => inner.edgeI(n.oParams(o), i, p) }
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lazy val paramsOut: Seq[Parameters] = (oPortMapping zip oBindings).flatMap { case ((s, e), b) => Seq.fill(e-s) { b._4 } }
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lazy val paramsIn: Seq[Parameters] = (iPortMapping zip iBindings).flatMap { case ((s, e), b) => Seq.fill(e-s) { b._4 } }
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// If you need access to the edges of a foreign Node, use this method (in/out create bundles)
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lazy val edges = (edgesIn, edgesOut)
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val flip = false // needed for blind nodes
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private def flipO(b: HeterogeneousBag[BO]) = if (flip) b.flip else b
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private def flipI(b: HeterogeneousBag[BI]) = if (flip) b else b.flip
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val wire = false // needed if you want to grab access to from inside a module
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private def wireO(b: HeterogeneousBag[BO]) = if (wire) Wire(b) else b
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private def wireI(b: HeterogeneousBag[BI]) = if (wire) Wire(b) else b
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protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map(e => Wire(outer.bundleO(e)))
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protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn .map(e => Wire(inner.bundleI(e)))
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lazy val bundleOut = wireO(flipO(HeterogeneousBag(edgesOut.map(outer.bundleO(_)))))
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lazy val bundleIn = wireI(flipI(HeterogeneousBag(edgesIn .map(inner.bundleI(_)))))
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protected[diplomacy] def danglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _), i) =>
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Dangle(
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source = HalfEdge(serial, i),
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sink = HalfEdge(n.serial, j),
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flipped= false,
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name = valName.name + "_out",
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data = bundleOut(i))
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}
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protected[diplomacy] def danglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _), i) =>
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Dangle(
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source = HalfEdge(n.serial, j),
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sink = HalfEdge(serial, i),
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flipped= true,
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name = valName.name + "_in",
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data = bundleIn(i))
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}
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// Used by LazyModules.module.instantiate
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private var bundlesSafeNow = false
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protected[diplomacy] def instantiate() = {
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bundlesSafeNow = true
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danglesOut ++ danglesIn
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}
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// Accessors to the result of negotiation to be used in LazyModuleImp:
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def out: Seq[(BO, EO)] = {
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require(bundlesSafeNow, s"${name}.out should only be called from the context of it's module implementation")
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bundleOut zip edgesOut
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}
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def in: Seq[(BI, EI)] = {
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require(bundlesSafeNow, s"${name}.in should only be called from the context of it's module implementation")
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bundleIn zip edgesIn
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}
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// connects the outward part of a node with the inward part of this node
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private def bind(h: OutwardNodeHandle[DI, UI, BI], binding: NodeBinding)
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@ -268,23 +296,7 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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case BIND_STAR => BIND_QUERY
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case BIND_QUERY => BIND_STAR })
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x.iPush(o, y, binding)
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def edges() = {
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val (iStart, iEnd) = x.iPortMapping(i)
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val (oStart, oEnd) = y.oPortMapping(o)
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require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
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Seq.tabulate(iEnd - iStart) { j => x.edgesIn(iStart+j) }
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}
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def bundles() = {
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val (iStart, iEnd) = x.iPortMapping(i)
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val (oStart, oEnd) = y.oPortMapping(o)
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require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
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Seq.tabulate(iEnd - iStart) { j =>
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(x.bundleIn(iStart+j), y.bundleOut(oStart+j))
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}
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}
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val (out, newbinding) = inner.connect(edges _, bundles _, p(MonitorsEnabled))
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LazyModule.stack.head.bindings = newbinding :: LazyModule.stack.head.bindings
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out
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None // !!! create monitors
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}
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override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] = bind(h, BIND_ONCE)
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@ -333,9 +345,6 @@ class MixedAdapterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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implicit valName: ValName)
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extends MixedNode(inner, outer)(num, num)
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{
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val externalIn: Boolean = true
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val externalOut: Boolean = true
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protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
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require (oStars + iStars <= 1, s"${name} (an adapter) appears left of a :*= ${iStars} times and right of a :=* ${oStars} times; at most once is allowed${lazyModule.line}")
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if (oStars > 0) {
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@ -356,6 +365,24 @@ class MixedAdapterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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}
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}
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class AdapterNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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dFn: D => D,
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uFn: U => U,
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num: Range.Inclusive = 0 to 999)(
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implicit valName: ValName)
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extends MixedAdapterNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, num)
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// IdentityNodes automatically connect their inputs to outputs
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class IdentityNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])()(implicit valName: ValName)
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extends AdapterNode(imp)({ s => s }, { s => s })
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{
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override protected[diplomacy] def instantiate() = {
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val dangles = super.instantiate()
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(out zip in) map { case ((o, _), (i, _)) => o <> i }
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dangles
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}
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}
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class MixedNexusNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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@ -369,9 +396,6 @@ class MixedNexusNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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// require (numPO.end >= 1, s"${name} does not accept outputs${lazyModule.line}")
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// require (numPI.end >= 1, s"${name} does not accept inputs${lazyModule.line}")
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val externalIn: Boolean = true
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val externalOut: Boolean = true
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protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
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require (iStars == 0, s"${name} (a nexus) appears left of :*= (perhaps you should flip the '*' to :=*?)${lazyModule.line}")
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require (oStars == 0, s"${name} (a nexus) appears right of a :=* (perhaps you should flip the '*' to :*=?)${lazyModule.line}")
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@ -381,13 +405,6 @@ class MixedNexusNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] = { val a = uFn(p); Seq.fill(n)(a) }
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}
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class AdapterNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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dFn: D => D,
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uFn: U => U,
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num: Range.Inclusive = 0 to 999)(
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implicit valName: ValName)
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extends MixedAdapterNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, num)
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class NexusNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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dFn: Seq[D] => D,
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uFn: Seq[U] => U,
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@ -396,30 +413,10 @@ class NexusNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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implicit valName: ValName)
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extends MixedNexusNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, numPO, numPI)
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class IdentityNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName)
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extends AdapterNode(imp)({s => s}, {s => s})
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class OutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName) extends IdentityNode(imp)
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{
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override val externalIn: Boolean = false
|
||||
override val externalOut: Boolean = true
|
||||
override lazy val bundleIn = bundleOut
|
||||
}
|
||||
|
||||
class InputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(implicit valName: ValName) extends IdentityNode(imp)
|
||||
{
|
||||
override val externalIn: Boolean = true
|
||||
override val externalOut: Boolean = false
|
||||
|
||||
override lazy val bundleOut = bundleIn
|
||||
}
|
||||
|
||||
// There are no Mixed SourceNodes
|
||||
class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName)
|
||||
extends MixedNode(imp, imp)(po.size to po.size, 0 to 0)
|
||||
{
|
||||
override val externalIn: Boolean = false
|
||||
override val externalOut: Boolean = true
|
||||
|
||||
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
|
||||
require (oStars <= 1, s"${name} (a source) appears right of a :=* ${oStars} times; at most once is allowed${lazyModule.line}")
|
||||
require (iStars == 0, s"${name} (a source) cannot appear left of a :*=${lazyModule.line}")
|
||||
@ -429,16 +426,12 @@ class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq
|
||||
}
|
||||
protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = po
|
||||
protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = Seq()
|
||||
|
||||
override lazy val bundleIn = { require(false, s"${name} has no bundleIn; try bundleOut?"); bundleOut }
|
||||
}
|
||||
|
||||
// There are no Mixed SinkNodes
|
||||
class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName)
|
||||
extends MixedNode(imp, imp)(0 to 0, pi.size to pi.size)
|
||||
{
|
||||
override val externalIn: Boolean = true
|
||||
override val externalOut: Boolean = false
|
||||
|
||||
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
|
||||
require (iStars <= 1, s"${name} (a sink) appears left of a :*= ${iStars} times; at most once is allowed${lazyModule.line}")
|
||||
require (oStars == 0, s"${name} (a sink) cannot appear right of a :=*${lazyModule.line}")
|
||||
@ -448,40 +441,4 @@ class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U
|
||||
}
|
||||
protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = Seq()
|
||||
protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = pi
|
||||
|
||||
override lazy val bundleOut = { require(false, s"${name} has no bundleOut; try bundleIn?"); bundleIn }
|
||||
}
|
||||
|
||||
class BlindOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName)
|
||||
extends SinkNode(imp)(pi)
|
||||
{
|
||||
override val externalIn: Boolean = false
|
||||
override val flip = true
|
||||
override lazy val bundleOut = bundleIn
|
||||
}
|
||||
|
||||
class BlindInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName)
|
||||
extends SourceNode(imp)(po)
|
||||
{
|
||||
override val externalOut: Boolean = false
|
||||
override val flip = true
|
||||
override lazy val bundleIn = bundleOut
|
||||
}
|
||||
|
||||
class InternalOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])(implicit valName: ValName)
|
||||
extends SinkNode(imp)(pi)
|
||||
{
|
||||
override val externalIn: Boolean = false
|
||||
override val externalOut: Boolean = false
|
||||
override val wire = true
|
||||
override lazy val bundleOut = bundleIn
|
||||
}
|
||||
|
||||
class InternalInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])(implicit valName: ValName)
|
||||
extends SourceNode(imp)(po)
|
||||
{
|
||||
override val externalIn: Boolean = false
|
||||
override val externalOut: Boolean = false
|
||||
override val wire = true
|
||||
override lazy val bundleIn = bundleOut
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user