riscv/rocket-chip
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diplomacy: change API to auto-create node bundles => cross-module refs

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This commit is contained in:
Wesley W. Terpstra
2017-09-13 18:06:03 -07:00
parent 53f6999ea8
commit 9217baf9d4
86 changed files with 575 additions and 933 deletions
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22
src/main/scala/devices/tilelink/BusBypass.scala
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@ -12,8 +12,8 @@ import scala.math.min
abstract class TLBusBypassBase(beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
protected val nodeIn = TLInputNode()
protected val nodeOut = TLOutputNode()
protected val nodeIn = TLIdentityNode()
protected val nodeOut = TLIdentityNode()
val node = NodeHandle(nodeIn, nodeOut)
protected val bar = LazyModule(new TLBusBypassBar)
@ -28,11 +28,9 @@ abstract class TLBusBypassBase(beatBytes: Int)(implicit p: Parameters) extends L
class TLBusBypass(beatBytes: Int)(implicit p: Parameters) extends TLBusBypassBase(beatBytes)
{
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = nodeIn.bundleIn
val out = nodeOut.bundleOut
val io = IO(new Bundle {
val bypass = Bool(INPUT)
}
})
bar.module.io.bypass := io.bypass
}
}
@ -47,17 +45,13 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
managerFn = { seq => seq(1) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
val io = IO(new Bundle {
val bypass = Bool(INPUT)
}
})
val in = io.in(0)
val out0 = io.out(0)
val out1 = io.out(1)
val (in, edge) = node.in(0)
val Seq((out0,_), (out1,_)) = node.out
val edge = node.edgesIn(0)
val bce = edge.manager.anySupportAcquireB && edge.client.anySupportProbe
// We need to be locked to the given bypass direction until all transactions stop