riscv/rocket-chip
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diplomacy: change API to auto-create node bundles => cross-module refs

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This commit is contained in:
Wesley W. Terpstra
2017-09-13 18:06:03 -07:00
parent 53f6999ea8
commit 9217baf9d4
86 changed files with 575 additions and 933 deletions
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62
src/main/scala/devices/debug/Debug.scala
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@ -288,14 +288,12 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.bundleOut.size
val nComponents = intnode.out.size
val io = new Bundle {
val io = IO(new Bundle {
val ctrl = (new DebugCtrlBundle(nComponents))
val tlIn = dmiNode.bundleIn
val debugInterrupts = intnode.bundleOut
val innerCtrl = new DecoupledIO(new DebugInternalBundle())
}
})
//----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it
// can be written even if 'Inner' is not being clocked or is in reset. This allows halting
@ -356,7 +354,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
debugIntNxt := debugIntRegs
for (component <- 0 until nComponents) {
io.debugInterrupts(component)(0) := debugIntRegs(component)
intnode.out(component)._1(0) := debugIntRegs(component)
}
// Halt request registers are set & cleared by writes to DMCONTROL.haltreq
@ -393,9 +391,9 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
val dmiXbar = LazyModule (new TLXbar())
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode = IntOutputNode()
val intnode = IntIdentityNode()
val dmiInnerNode = TLAsyncOutputNode()
val dmiInnerNode = TLAsyncIdentityNode()
intnode :*= dmOuter.intnode
@ -405,15 +403,13 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.bundleOut.size
val nComponents = intnode.out.size
val io = new Bundle {
val io = IO(new Bundle {
val dmi = new DMIIO()(p).flip()
val dmiInner = dmiInnerNode.bundleOut
val ctrl = new DebugCtrlBundle(nComponents)
val debugInterrupts = intnode.bundleOut
val innerCtrl = new AsyncBundle(depth=1, new DebugInternalBundle())
}
})
dmi2tl.module.io.dmi <> io.dmi
@ -447,13 +443,11 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
val nComponents = getNComponents()
val io = new Bundle {
val hart_in = tlNode.bundleIn
val dmi_in = dmiNode.bundleIn
val io = IO(new Bundle {
val dmactive = Bool(INPUT)
val innerCtrl = (new DecoupledIO(new DebugInternalBundle())).flip
val debugUnavail = Vec(nComponents, Bool()).asInput
}
})
//--------------------------------------------------------------
// Import constants for shorter variable names
@ -1012,25 +1006,23 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implicit p: Parameters) extends LazyModule{
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents)(p))
val dmiNode = TLAsyncInputNode()
val tlNode = TLInputNode()
val dmiNode = TLAsyncIdentityNode()
val tlNode = TLIdentityNode()
dmInner.dmiNode := TLAsyncCrossingSink(depth=1)(dmiNode)
dmInner.tlNode := tlNode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = IO(new Bundle {
// this comes from tlClk domain.
val tl_in = tlNode.bundleIn
// These are all asynchronous and come from Outer
val dmi_in = dmiNode.bundleIn
val dmactive = Bool(INPUT)
val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip
// This comes from tlClk domain.
val debugUnavail = Vec(getNComponents(), Bool()).asInput
val psd = new PSDTestMode().asInput
}
})
dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl)
dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd)
@ -1049,26 +1041,24 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
override val alwaysExtended = true
}
val node = TLInputNode()
val intnode = IntOutputNode()
val node = TLIdentityNode()
val intnode = IntIdentityNode()
val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.bundleOut.size})(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.edges._2.size})(p))
dmInner.dmiNode := dmOuter.dmiInnerNode
dmInner.tlNode := node
intnode :*= dmOuter.intnode
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.bundleOut.size
val nComponents = intnode.out.size
val io = new Bundle {
val io = IO(new Bundle {
val ctrl = new DebugCtrlBundle(nComponents)
val dmi = new ClockedDMIIO().flip
val in = node.bundleIn
val debugInterrupts = intnode.bundleOut
val psd = new PSDTestMode().asInput
}
})
dmOuter.module.io.dmi <> io.dmi.dmi
dmOuter.module.reset := io.dmi.dmiReset
@ -1102,16 +1092,14 @@ class ClockedDMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p){
class DMIToTL(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(TLClientParameters("debug"))
val node = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters("debug")))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = IO(new Bundle {
val dmi = new DMIIO()(p).flip()
val out = node.bundleOut
}
})
val tl = io.out(0)
val edge = node.edgesOut(0)
val (tl, edge) = node.out(0)
val src = Wire(init = 0.U)
val addr = Wire(init = (io.dmi.req.bits.addr << 2))

4
src/main/scala/devices/debug/Periphery.scala
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@ -54,9 +54,9 @@ trait HasPeripheryDebugBundle {
}
debug.psd.foreach { _ <> psd }
}
}
trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
trait HasPeripheryDebugModuleImp extends LazyModuleImp with HasPeripheryDebugBundle {
val outer: HasPeripheryDebug
val debug = IO(new DebugIO)