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diplomacy: change API to auto-create node bundles => cross-module refs

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This commit is contained in:
Wesley W. Terpstra
2017-09-13 18:06:03 -07:00
parent 53f6999ea8
commit 9217baf9d4
86 changed files with 575 additions and 933 deletions
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62
src/main/scala/devices/debug/Debug.scala
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@ -288,14 +288,12 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.bundleOut.size
val nComponents = intnode.out.size
val io = new Bundle {
val io = IO(new Bundle {
val ctrl = (new DebugCtrlBundle(nComponents))
val tlIn = dmiNode.bundleIn
val debugInterrupts = intnode.bundleOut
val innerCtrl = new DecoupledIO(new DebugInternalBundle())
}
})
//----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it
// can be written even if 'Inner' is not being clocked or is in reset. This allows halting
@ -356,7 +354,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
debugIntNxt := debugIntRegs
for (component <- 0 until nComponents) {
io.debugInterrupts(component)(0) := debugIntRegs(component)
intnode.out(component)._1(0) := debugIntRegs(component)
}
// Halt request registers are set & cleared by writes to DMCONTROL.haltreq
@ -393,9 +391,9 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
val dmiXbar = LazyModule (new TLXbar())
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode = IntOutputNode()
val intnode = IntIdentityNode()
val dmiInnerNode = TLAsyncOutputNode()
val dmiInnerNode = TLAsyncIdentityNode()
intnode :*= dmOuter.intnode
@ -405,15 +403,13 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.bundleOut.size
val nComponents = intnode.out.size
val io = new Bundle {
val io = IO(new Bundle {
val dmi = new DMIIO()(p).flip()
val dmiInner = dmiInnerNode.bundleOut
val ctrl = new DebugCtrlBundle(nComponents)
val debugInterrupts = intnode.bundleOut
val innerCtrl = new AsyncBundle(depth=1, new DebugInternalBundle())
}
})
dmi2tl.module.io.dmi <> io.dmi
@ -447,13 +443,11 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
val nComponents = getNComponents()
val io = new Bundle {
val hart_in = tlNode.bundleIn
val dmi_in = dmiNode.bundleIn
val io = IO(new Bundle {
val dmactive = Bool(INPUT)
val innerCtrl = (new DecoupledIO(new DebugInternalBundle())).flip
val debugUnavail = Vec(nComponents, Bool()).asInput
}
})
//--------------------------------------------------------------
// Import constants for shorter variable names
@ -1012,25 +1006,23 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implicit p: Parameters) extends LazyModule{
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents)(p))
val dmiNode = TLAsyncInputNode()
val tlNode = TLInputNode()
val dmiNode = TLAsyncIdentityNode()
val tlNode = TLIdentityNode()
dmInner.dmiNode := TLAsyncCrossingSink(depth=1)(dmiNode)
dmInner.tlNode := tlNode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = IO(new Bundle {
// this comes from tlClk domain.
val tl_in = tlNode.bundleIn
// These are all asynchronous and come from Outer
val dmi_in = dmiNode.bundleIn
val dmactive = Bool(INPUT)
val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip
// This comes from tlClk domain.
val debugUnavail = Vec(getNComponents(), Bool()).asInput
val psd = new PSDTestMode().asInput
}
})
dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl)
dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd)
@ -1049,26 +1041,24 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
override val alwaysExtended = true
}
val node = TLInputNode()
val intnode = IntOutputNode()
val node = TLIdentityNode()
val intnode = IntIdentityNode()
val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.bundleOut.size})(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.edges._2.size})(p))
dmInner.dmiNode := dmOuter.dmiInnerNode
dmInner.tlNode := node
intnode :*= dmOuter.intnode
lazy val module = new LazyModuleImp(this) {
val nComponents = intnode.bundleOut.size
val nComponents = intnode.out.size
val io = new Bundle {
val io = IO(new Bundle {
val ctrl = new DebugCtrlBundle(nComponents)
val dmi = new ClockedDMIIO().flip
val in = node.bundleIn
val debugInterrupts = intnode.bundleOut
val psd = new PSDTestMode().asInput
}
})
dmOuter.module.io.dmi <> io.dmi.dmi
dmOuter.module.reset := io.dmi.dmiReset
@ -1102,16 +1092,14 @@ class ClockedDMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p){
class DMIToTL(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(TLClientParameters("debug"))
val node = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters("debug")))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = IO(new Bundle {
val dmi = new DMIIO()(p).flip()
val out = node.bundleOut
}
})
val tl = io.out(0)
val edge = node.edgesOut(0)
val (tl, edge) = node.out(0)
val src = Wire(init = 0.U)
val addr = Wire(init = (io.dmi.req.bits.addr << 2))

4
src/main/scala/devices/debug/Periphery.scala
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@ -54,9 +54,9 @@ trait HasPeripheryDebugBundle {
}
debug.psd.foreach { _ <> psd }
}
}
trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
trait HasPeripheryDebugModuleImp extends LazyModuleImp with HasPeripheryDebugBundle {
val outer: HasPeripheryDebug
val debug = IO(new DebugIO)

25
src/main/scala/devices/tilelink/BootROM.scala
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@ -23,25 +23,22 @@ case object BootROMParams extends Field[BootROMParams]
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
{
val node = TLManagerNode(beatBytes, TLManagerParameters (
address = List(AddressSet(base, size-1)),
resources = resources,
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0)))
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(AddressSet(base, size-1)),
resources = resources,
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0))),
beatBytes = beatBytes)))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
val contents = contentsDelayed
val wrapSize = 1 << log2Ceil(contents.size)
require (wrapSize <= size)
val in = io.in(0)
val edge = node.edgesIn(0)
val (in, edge) = node.in(0)
val words = (contents ++ Seq.fill(wrapSize-contents.size)(0.toByte)).grouped(beatBytes).toSeq
val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8})
@ -78,7 +75,7 @@ trait HasPeripheryBootROM extends HasPeripheryBus {
}
/** Coreplex will power-on running at 0x10040 (BootROM) */
trait HasPeripheryBootROMModuleImp extends LazyMultiIOModuleImp
trait HasPeripheryBootROMModuleImp extends LazyModuleImp
with HasResetVectorWire {
val outer: HasPeripheryBootROM
global_reset_vector := outer.resetVector.U

11
src/main/scala/devices/tilelink/BusBlocker.scala
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@ -81,20 +81,13 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
beatBytes = params.controlBeatBytes)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val ctl = controlNode.bundleIn
val in = nodeIn.bundleIn
val out = nodeOut.bundleOut
}
// We need to be able to represent +1 larger than the largest populated address
val addressBits = log2Ceil(nodeOut.edgesOut(0).manager.maxAddress+1+1)
val addressBits = log2Ceil(nodeOut.out(0)._2.manager.maxAddress+1+1)
val pmps = RegInit(Vec.fill(params.pmpRegisters) { DevicePMP(addressBits, params.pageBits) })
val blocks = pmps.tail.map(_.blockPriorAddress) :+ Bool(false)
controlNode.regmap(0 -> (pmps zip blocks).map { case (p, b) => p.fields(b) }.toList.flatten)
val in = io.in(0)
val edge = nodeIn.edgesIn(0)
val (in, edge) = nodeIn.in(0)
// Determine if a request is allowed
val needW = in.a.bits.opcode =/= TLMessages.Get

22
src/main/scala/devices/tilelink/BusBypass.scala
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@ -12,8 +12,8 @@ import scala.math.min
abstract class TLBusBypassBase(beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
protected val nodeIn = TLInputNode()
protected val nodeOut = TLOutputNode()
protected val nodeIn = TLIdentityNode()
protected val nodeOut = TLIdentityNode()
val node = NodeHandle(nodeIn, nodeOut)
protected val bar = LazyModule(new TLBusBypassBar)
@ -28,11 +28,9 @@ abstract class TLBusBypassBase(beatBytes: Int)(implicit p: Parameters) extends L
class TLBusBypass(beatBytes: Int)(implicit p: Parameters) extends TLBusBypassBase(beatBytes)
{
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = nodeIn.bundleIn
val out = nodeOut.bundleOut
val io = IO(new Bundle {
val bypass = Bool(INPUT)
}
})
bar.module.io.bypass := io.bypass
}
}
@ -47,17 +45,13 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
managerFn = { seq => seq(1) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
val io = IO(new Bundle {
val bypass = Bool(INPUT)
}
})
val in = io.in(0)
val out0 = io.out(0)
val out1 = io.out(1)
val (in, edge) = node.in(0)
val Seq((out0,_), (out1,_)) = node.out
val edge = node.edgesIn(0)
val bce = edge.manager.anySupportAcquireB && edge.client.anySupportProbe
// We need to be locked to the given bypass direction until all transactions stop

10
src/main/scala/devices/tilelink/Clint.scala
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@ -53,11 +53,9 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = IO(new Bundle {
val rtcTick = Bool(INPUT)
val int = intnode.bundleOut
val in = node.bundleIn
}
})
val time = Seq.fill(timeWidth/regWidth)(Reg(init=UInt(0, width = regWidth)))
when (io.rtcTick) {
@ -66,11 +64,11 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
reg := newTime >> i
}
val nTiles = intnode.edgesOut.size
val nTiles = intnode.out.size
val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
io.int.zipWithIndex.foreach { case (int, i) =>
intnode.in.map(_._1).zipWithIndex.foreach { case (int, i) =>
int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
}

7
src/main/scala/devices/tilelink/Error.scala
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@ -40,15 +40,10 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
minLatency = 1))) // no bypass needed for this device
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
import TLMessages._
import TLPermissions._
val edge = node.edgesIn(0)
val in = io.in(0)
val (in, edge) = node.in(0)
val a = Queue(in.a, 1)
val c = Queue(in.c, 1)
val da = Wire(in.d)

23
src/main/scala/devices/tilelink/MaskROM.scala
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@ -24,21 +24,18 @@ trait HasPeripheryMaskROMSlave extends HasPeripheryBus {
class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
val beatBytes = c.width/8
val node = TLManagerNode(beatBytes, TLManagerParameters(
address = AddressSet.misaligned(c.address, c.depth*beatBytes),
resources = new SimpleDevice("rom", Seq("sifive,maskrom0")).reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0))) // requests are handled in order
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = AddressSet.misaligned(c.address, c.depth*beatBytes),
resources = new SimpleDevice("rom", Seq("sifive,maskrom0")).reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes)))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
val in = io.in(0)
val edge = node.edgesIn(0)
val (in, edge)= node.in(0)
val rom = ROMGenerator(ROMConfig(c.name, c.depth, c.width))
rom.io.clock := clock

17
src/main/scala/devices/tilelink/Plic.scala
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@ -91,12 +91,12 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
/* Negotiated sizes */
def nDevices: Int = intnode.edgesIn.map(_.source.num).sum
def nDevices: Int = intnode.in.map(_._2.source.num).sum
def nPriorities = min(params.maxPriorities, nDevices)
def nHarts = intnode.edgesOut.map(_.source.num).sum
def nHarts = intnode.out.map(_._2.source.num).sum
// Assign all the devices unique ranges
lazy val sources = intnode.edgesIn.map(_.source)
lazy val sources = intnode.in.map(_._2.source)
lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten
@ -109,16 +109,13 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
}
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val tl_in = node.bundleIn
val devices = intnode.bundleIn
val harts = intnode.bundleOut
}
val (io_devices, edgesIn) = intnode.in.unzip
val (io_harts, _) = intnode.out.unzip
// Compact the interrupt vector the same way
val interrupts = (intnode.edgesIn zip io.devices).map { case (e, i) => i.take(e.source.num) }.flatten
val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
val harts = io.harts.flatten
val harts = io_harts.flatten
println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
flatSources.foreach { s =>

9
src/main/scala/devices/tilelink/TestRAM.scala
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@ -29,16 +29,11 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
require ((address.mask & (beatBytes-1)) == beatBytes-1)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
val mask = bigBits(address.mask >> log2Ceil(beatBytes))
val in = io.in(0)
val edge = node.edgesIn(0)
val (in, edge) = node.in(0)
val addrBits = (mask zip edge.addr_hi(in.a.bits).toBools).filter(_._1).map(_._2)
val memAddress = Cat(addrBits.reverse)
@ -75,7 +70,7 @@ class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) exten
model.node := fuzz.node
ram.node := TLDelayer(0.25)(model.node)
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}

7
src/main/scala/devices/tilelink/Zero.scala
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@ -24,12 +24,7 @@ class TLZero(address: AddressSet, resources: Seq[Resource], executable: Boolean
minLatency = 1))) // no bypass needed for this device
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
val in = io.in(0)
val edge = node.edgesIn(0)
val (in, edge) = node.in(0)
val a = Queue(in.a, 2)
val hasData = edge.hasData(a.bits)