diplomacy: change API to auto-create node bundles => cross-module refs

src/main/scala/coreplex/BaseCoreplex.scala

@@ -21,7 +21,7 @@ abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with Bind
   lazy val json = JSON(bindingTree)
 }
 
-abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyMultiIOModuleImp(_outer) {
+abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyModuleImp(_outer) {
   val outer = _outer
   ElaborationArtefacts.add("graphml", outer.graphML)
   ElaborationArtefacts.add("dts", outer.dts)

src/main/scala/coreplex/InterruptBus.scala

@@ -44,7 +44,7 @@ abstract trait HasExtInterrupts extends HasInterruptBus {
   }
 
   val nExtInterrupts = p(NExtTopInterrupts)
-  val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
+  val extInterrupts = IntSourceNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
 }
 
 /** This trait should be used if the External Interrupts have NOT
@@ -77,9 +77,9 @@ trait HasExtInterruptsBundle {
 /** This trait performs the translation from a UInt IO into Diplomatic Interrupts.
   * The wiring must be done in the concrete LazyModuleImp. 
   */
-trait HasExtInterruptsModuleImp extends LazyMultiIOModuleImp with HasExtInterruptsBundle {
+trait HasExtInterruptsModuleImp extends LazyModuleImp with HasExtInterruptsBundle {
   val outer: HasExtInterrupts
   val interrupts = IO(UInt(INPUT, width = outer.nExtInterrupts))
 
-  outer.extInterrupts.bundleIn.flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) }
+  outer.extInterrupts.in.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) }
 }

src/main/scala/coreplex/Ports.scala

@@ -33,7 +33,7 @@ trait HasMasterAXI4MemPort extends HasMemoryBus {
   private val params = p(ExtMem)
   private val device = new MemoryDevice
 
-  val mem_axi4 = AXI4BlindOutputNode(Seq.tabulate(nMemoryChannels) { channel =>
+  val mem_axi4 = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel =>
     val base = AddressSet(params.base, params.size-1)
     val filter = AddressSet(channel * cacheBlockBytes, ~((nMemoryChannels-1) * cacheBlockBytes))
 
@@ -77,9 +77,10 @@ trait HasMasterAXI4MemPortBundle {
 }
 
 /** Actually generates the corresponding IO in the concrete Module */
-trait HasMasterAXI4MemPortModuleImp extends LazyMultiIOModuleImp with HasMasterAXI4MemPortBundle {
+trait HasMasterAXI4MemPortModuleImp extends LazyModuleImp with HasMasterAXI4MemPortBundle {
   val outer: HasMasterAXI4MemPort
-  val mem_axi4 = IO(outer.mem_axi4.bundleOut)
+  val mem_axi4 = IO(HeterogeneousBag(outer.mem_axi4.in.map(_._1.cloneType)))
+  (mem_axi4 zip outer.mem_axi4.in) foreach { case (i, (o, _)) => i <> o }
   val nMemoryChannels = outer.nMemoryChannels
 }
 
@@ -87,7 +88,7 @@ trait HasMasterAXI4MemPortModuleImp extends LazyMultiIOModuleImp with HasMasterA
 trait HasMasterAXI4MMIOPort extends HasSystemBus {
   private val params = p(ExtBus)
   private val device = new SimpleBus("mmio", Nil)
-  val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
+  val mmio_axi4 = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address       = List(AddressSet(params.base, params.size-1)),
       resources     = device.ranges,
@@ -116,15 +117,16 @@ trait HasMasterAXI4MMIOPortBundle {
 }
 
 /** Actually generates the corresponding IO in the concrete Module */
-trait HasMasterAXI4MMIOPortModuleImp extends LazyMultiIOModuleImp with HasMasterAXI4MMIOPortBundle {
+trait HasMasterAXI4MMIOPortModuleImp extends LazyModuleImp with HasMasterAXI4MMIOPortBundle {
   val outer: HasMasterAXI4MMIOPort
-  val mmio_axi4 = IO(outer.mmio_axi4.bundleOut)
+  val mmio_axi4 = IO(HeterogeneousBag(outer.mmio_axi4.in.map(_._1.cloneType)))
+  (mmio_axi4 zip outer.mmio_axi4.in) foreach { case (i, (o, _)) => i <> o }
 }
 
 /** Adds an AXI4 port to the system intended to be a slave on an MMIO device bus */
 trait HasSlaveAXI4Port extends HasSystemBus {
   private val params = p(ExtIn)
-  val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
+  val l2FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
     masters = Seq(AXI4MasterParameters(
       name = "AXI4 periphery",
       id   = IdRange(0, 1 << params.idBits))))))
@@ -155,16 +157,17 @@ trait HasSlaveAXI4PortBundle {
 }
 
 /** Actually generates the corresponding IO in the concrete Module */
-trait HasSlaveAXI4PortModuleImp extends LazyMultiIOModuleImp with HasSlaveAXI4PortBundle {
+trait HasSlaveAXI4PortModuleImp extends LazyModuleImp with HasSlaveAXI4PortBundle {
   val outer: HasSlaveAXI4Port
-  val l2_frontend_bus_axi4 = IO(outer.l2FrontendAXI4Node.bundleIn)
+  val l2_frontend_bus_axi4 = IO(HeterogeneousBag(outer.l2FrontendAXI4Node.out.map(_._1.cloneType)).flip)
+  (outer.l2FrontendAXI4Node.out zip l2_frontend_bus_axi4) foreach { case ((i, _), o) => i <> o }
 }
 
 /** Adds a TileLink port to the system intended to master an MMIO device bus */
 trait HasMasterTLMMIOPort extends HasSystemBus {
   private val params = p(ExtBus)
   private val device = new SimpleBus("mmio", Nil)
-  val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
+  val mmio_tl = TLManagerNode(Seq(TLManagerPortParameters(
     managers = Seq(TLManagerParameters(
       address            = List(AddressSet(params.base, params.size-1)),
       resources          = device.ranges,
@@ -196,9 +199,10 @@ trait HasMasterTLMMIOPortBundle {
 }
 
 /** Actually generates the corresponding IO in the concrete Module */
-trait HasMasterTLMMIOPortModuleImp extends LazyMultiIOModuleImp with HasMasterTLMMIOPortBundle {
+trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPortBundle {
   val outer: HasMasterTLMMIOPort
-  val mmio_tl = IO(outer.mmio_tl.bundleOut)
+  val mmio_tl = IO(HeterogeneousBag(outer.mmio_tl.in.map(_._1.cloneType)))
+  (mmio_tl zip outer.mmio_tl.out) foreach { case (i, (o, _)) => i <> o }
 }
 
 /** Adds an TL port to the system intended to be a slave on an MMIO device bus.
@@ -206,7 +210,7 @@ trait HasMasterTLMMIOPortModuleImp extends LazyMultiIOModuleImp with HasMasterTL
   */
 trait HasSlaveTLPort extends HasSystemBus {
   private val params = p(ExtIn)
-  val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters(
+  val l2FrontendTLNode = TLClientNode(Seq(TLClientPortParameters(
     clients = Seq(TLClientParameters(
       name     = "Front Port (TL)",
       sourceId = IdRange(0, 1 << params.idBits))))))
@@ -233,9 +237,10 @@ trait HasSlaveTLPortBundle {
 }
 
 /** Actually generates the corresponding IO in the concrete Module */
-trait HasSlaveTLPortModuleImp extends LazyMultiIOModuleImp with HasSlaveTLPortBundle {
+trait HasSlaveTLPortModuleImp extends LazyModuleImp with HasSlaveTLPortBundle {
   val outer: HasSlaveTLPort
-  val l2_frontend_bus_tl = IO(outer.l2FrontendTLNode.bundleIn)
+  val l2_frontend_bus_tl = IO(HeterogeneousBag(outer.l2FrontendTLNode.out.map(_._1.cloneType)).flip)
+  (outer.l2FrontendTLNode.in zip l2_frontend_bus_tl) foreach { case ((i, _), o) => i <> o }
 }
 
 /** Memory with AXI port for use in elaboratable test harnesses. */
@@ -245,7 +250,7 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
   val size = totalSize / channels
   require(totalSize % channels == 0)
 
-  val node = AXI4BlindInputNode(Seq.fill(channels) {
+  val node = AXI4MasterNode(Seq.fill(channels) {
     AXI4MasterPortParameters(Seq(AXI4MasterParameters(
       name = "dut",
       id   = IdRange(0, 1 << config.idBits)
@@ -258,8 +263,9 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
   }
 
   lazy val module = new LazyModuleImp(this) {
-    val io = new Bundle {
-      val axi4 = node.bundleIn
-    }
+    val io = IO(new Bundle {
+      val axi4 = HeterogeneousBag(node.out.map(_._1.cloneType)).flip
+    })
+    (node.out zip io.axi4) foreach { case ((i, _), o) => i <> o }
   }
 }

src/main/scala/coreplex/RTC.scala

@@ -3,10 +3,10 @@
 package freechips.rocketchip.coreplex
 
 import Chisel._
-import freechips.rocketchip.diplomacy.{LazyMultiIOModuleImp, DTSTimebase}
+import freechips.rocketchip.diplomacy.{LazyModuleImp, DTSTimebase}
 import freechips.rocketchip.devices.tilelink.HasPeripheryClint
 
-trait HasRTCModuleImp extends LazyMultiIOModuleImp {
+trait HasRTCModuleImp extends LazyModuleImp {
   val outer: HasPeripheryClint
   private val pbusFreq = outer.p(PeripheryBusKey).frequency
   private val rtcFreq = outer.p(DTSTimebase)

src/main/scala/coreplex/RocketCoreplex.scala

@@ -98,7 +98,7 @@ trait HasRocketTilesBundle {
   val rocket_tile_inputs: Vec[ClockedRocketTileInputs]
 }
 
-trait HasRocketTilesModuleImp extends LazyMultiIOModuleImp
+trait HasRocketTilesModuleImp extends LazyModuleImp
     with HasRocketTilesBundle
     with HasResetVectorWire
     with HasPeripheryDebugModuleImp {

src/main/scala/coreplex/SystemBus.scala

@@ -22,7 +22,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   private val master_splitter = LazyModule(new TLSplitter)  // Allows cycle-free connection to external networks
   master_splitter.suggestName(s"${busName}_master_TLSplitter")
   inwardNode :=* master_splitter.node
-  def busView = master_splitter.node.edgesIn.head
+  def busView = master_splitter.node.in.head._2
 
   protected def inwardSplitNode: TLInwardNode = master_splitter.node
   protected def outwardSplitNode: TLOutwardNode = master_splitter.node