riscv/rocket-chip
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diplomacy: change API to auto-create node bundles => cross-module refs

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This commit is contained in:
Wesley W. Terpstra
2017-09-13 18:06:03 -07:00
parent 53f6999ea8
commit 9217baf9d4
86 changed files with 575 additions and 933 deletions
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17
src/main/scala/amba/ahb/Nodes.scala
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@ -4,12 +4,13 @@ package freechips.rocketchip.amba.ahb
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBEdgeParameters, AHBBundle]
{
def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu)
def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu)
def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p)
def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p)
def bundleO(eo: AHBEdgeParameters): AHBBundle = AHBBundle(eo.bundle)
def bundleI(ei: AHBEdgeParameters): AHBBundle = AHBBundle(ei.bundle)
@ -25,7 +26,6 @@ object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, A
}
// Nodes implemented inside modules
case class AHBIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImp)
case class AHBMasterNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends SourceNode(AHBImp)(portParams)
case class AHBSlaveNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImp)(portParams)
case class AHBNexusNode(
@ -36,13 +36,4 @@ case class AHBNexusNode(
implicit valName: ValName)
extends NexusNode(AHBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
// Nodes passed from an inner module
case class AHBOutputNode()(implicit valName: ValName) extends OutputNode(AHBImp)
case class AHBInputNode()(implicit valName: ValName) extends InputNode(AHBImp)
// Nodes used for external ports
case class AHBBlindOutputNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(AHBImp)(portParams)
case class AHBBlindInputNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends BlindInputNode(AHBImp)(portParams)
case class AHBInternalOutputNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(AHBImp)(portParams)
case class AHBInternalInputNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends InternalInputNode(AHBImp)(portParams)
case class AHBIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImp)()

4
src/main/scala/amba/ahb/Parameters.scala
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@ -3,6 +3,7 @@
package freechips.rocketchip.amba.ahb
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import scala.math.max
@ -90,7 +91,8 @@ object AHBBundleParameters
case class AHBEdgeParameters(
master: AHBMasterPortParameters,
slave: AHBSlavePortParameters)
slave: AHBSlavePortParameters,
params: Parameters)
{
val bundle = AHBBundleParameters(master, slave)
}

12
src/main/scala/amba/ahb/RegisterRouter.scala
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@ -24,7 +24,7 @@ case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes:
// Calling this method causes the matching AHB bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val ahb = bundleIn(0)
val (ahb, _) = this.in(0)
val indexBits = log2Up((address.mask+1)/beatBytes)
val params = RegMapperParams(indexBits, beatBytes, 1)
@ -76,13 +76,11 @@ abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concu
val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts))
}
case class AHBRegBundleArg(interrupts: HeterogeneousBag[Vec[Bool]], in: HeterogeneousBag[AHBBundle])(implicit val p: Parameters)
case class AHBRegBundleArg()(implicit val p: Parameters)
class AHBRegBundleBase(arg: AHBRegBundleArg) extends Bundle
{
implicit val p = arg.p
val interrupts = arg.interrupts
val in = arg.in
}
class AHBRegBundle[P](val params: P, arg: AHBRegBundleArg) extends AHBRegBundleBase(arg)
@ -90,8 +88,8 @@ class AHBRegBundle[P](val params: P, arg: AHBRegBundleArg) extends AHBRegBundleB
class AHBRegModule[P, B <: AHBRegBundleBase](val params: P, bundleBuilder: => B, router: AHBRegisterRouterBase)
extends LazyModuleImp(router) with HasRegMap
{
val io = bundleBuilder
val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
val io = IO(bundleBuilder)
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
}
@ -104,5 +102,5 @@ class AHBRegisterRouter[B <: AHBRegBundleBase, M <: LazyModuleImp]
require (isPow2(size))
// require (size >= 4096) ... not absolutely required, but highly recommended
lazy val module = moduleBuilder(bundleBuilder(AHBRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
lazy val module = moduleBuilder(bundleBuilder(AHBRegBundleArg()), this)
}

6
src/main/scala/amba/ahb/SRAM.scala
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@ -22,15 +22,11 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
require ((address.mask & (beatBytes-1)) == beatBytes-1)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
val mask = bigBits(address.mask >> log2Ceil(beatBytes))
val in = io.in(0)
val (in, _) = node.in(0)
// The mask and address during the address phase
val a_access = in.htrans === AHBParameters.TRANS_NONSEQ || in.htrans === AHBParameters.TRANS_SEQ

19
src/main/scala/amba/ahb/Test.scala
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@ -30,7 +30,7 @@ class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
ram.node := xbar.node
gpio.node := xbar.node
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
@ -42,7 +42,7 @@ class AHBNativeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(imp
class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
{
val node = AHBOutputNode()
val node = AHBIdentityNode()
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
@ -55,10 +55,9 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
model.node))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val out = node.bundleOut
val io = IO(new Bundle {
val finished = Bool(OUTPUT)
}
})
io.finished := fuzz.module.io.finished
}
@ -66,7 +65,7 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
{
val node = AHBInputNode()
val node = AHBIdentityNode()
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
ram.node :=
@ -77,11 +76,7 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
AHBToTL()(
node)))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
}
lazy val module = new LazyModuleImp(this) { }
}
class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
@ -91,7 +86,7 @@ class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
slave.node := master.node
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := master.module.io.finished
}
}

7
src/main/scala/amba/ahb/ToTL.scala
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@ -41,12 +41,7 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
val node = AHBToTLNode()
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val beatBytes = edgeOut.manager.beatBytes
val d_send = RegInit(Bool(false))

22
src/main/scala/amba/ahb/Xbar.scala
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@ -16,35 +16,31 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
// Require consistent bus widths
val port0 = node.edgesOut(0).slave
node.edgesOut.foreach { edge =>
val (io_out, edgesOut) = node.out.unzip
val port0 = edgesOut(0).slave
edgesOut.foreach { edge =>
val port = edge.slave
require (port.beatBytes == port0.beatBytes,
s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}")
}
val port_addrs = node.edgesOut.map(_.slave.slaves.map(_.address).flatten)
val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten)
val routingMask = AddressDecoder(port_addrs)
val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
val in = io.in(0)
val (in, _) = node.in(0)
val a_sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.haddr)).reduce(_ || _)))
val d_sel = Reg(a_sel)
when (in.hready) { d_sel := a_sel }
(a_sel zip io.out) foreach { case (sel, out) =>
(a_sel zip io_out) foreach { case (sel, out) =>
out := in
out.hsel := in.hsel && sel
}
in.hreadyout := !Mux1H(d_sel, io.out.map(!_.hreadyout))
in.hresp := Mux1H(d_sel, io.out.map(_.hresp))
in.hrdata := Mux1H(d_sel, io.out.map(_.hrdata))
in.hreadyout := !Mux1H(d_sel, io_out.map(!_.hreadyout))
in.hresp := Mux1H(d_sel, io_out.map(_.hresp))
in.hrdata := Mux1H(d_sel, io_out.map(_.hrdata))
}
}