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diplomacy: change API to auto-create node bundles => cross-module refs

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This commit is contained in:
Wesley W. Terpstra
2017-09-13 18:06:03 -07:00
parent 53f6999ea8
commit 9217baf9d4
86 changed files with 575 additions and 933 deletions
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17
src/main/scala/amba/ahb/Nodes.scala
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@ -4,12 +4,13 @@ package freechips.rocketchip.amba.ahb
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBEdgeParameters, AHBBundle]
{
def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu)
def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu)
def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p)
def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p)
def bundleO(eo: AHBEdgeParameters): AHBBundle = AHBBundle(eo.bundle)
def bundleI(ei: AHBEdgeParameters): AHBBundle = AHBBundle(ei.bundle)
@ -25,7 +26,6 @@ object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, A
}
// Nodes implemented inside modules
case class AHBIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImp)
case class AHBMasterNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends SourceNode(AHBImp)(portParams)
case class AHBSlaveNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImp)(portParams)
case class AHBNexusNode(
@ -36,13 +36,4 @@ case class AHBNexusNode(
implicit valName: ValName)
extends NexusNode(AHBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
// Nodes passed from an inner module
case class AHBOutputNode()(implicit valName: ValName) extends OutputNode(AHBImp)
case class AHBInputNode()(implicit valName: ValName) extends InputNode(AHBImp)
// Nodes used for external ports
case class AHBBlindOutputNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(AHBImp)(portParams)
case class AHBBlindInputNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends BlindInputNode(AHBImp)(portParams)
case class AHBInternalOutputNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(AHBImp)(portParams)
case class AHBInternalInputNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends InternalInputNode(AHBImp)(portParams)
case class AHBIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImp)()

4
src/main/scala/amba/ahb/Parameters.scala
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@ -3,6 +3,7 @@
package freechips.rocketchip.amba.ahb
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import scala.math.max
@ -90,7 +91,8 @@ object AHBBundleParameters
case class AHBEdgeParameters(
master: AHBMasterPortParameters,
slave: AHBSlavePortParameters)
slave: AHBSlavePortParameters,
params: Parameters)
{
val bundle = AHBBundleParameters(master, slave)
}

12
src/main/scala/amba/ahb/RegisterRouter.scala
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@ -24,7 +24,7 @@ case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes:
// Calling this method causes the matching AHB bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val ahb = bundleIn(0)
val (ahb, _) = this.in(0)
val indexBits = log2Up((address.mask+1)/beatBytes)
val params = RegMapperParams(indexBits, beatBytes, 1)
@ -76,13 +76,11 @@ abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concu
val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts))
}
case class AHBRegBundleArg(interrupts: HeterogeneousBag[Vec[Bool]], in: HeterogeneousBag[AHBBundle])(implicit val p: Parameters)
case class AHBRegBundleArg()(implicit val p: Parameters)
class AHBRegBundleBase(arg: AHBRegBundleArg) extends Bundle
{
implicit val p = arg.p
val interrupts = arg.interrupts
val in = arg.in
}
class AHBRegBundle[P](val params: P, arg: AHBRegBundleArg) extends AHBRegBundleBase(arg)
@ -90,8 +88,8 @@ class AHBRegBundle[P](val params: P, arg: AHBRegBundleArg) extends AHBRegBundleB
class AHBRegModule[P, B <: AHBRegBundleBase](val params: P, bundleBuilder: => B, router: AHBRegisterRouterBase)
extends LazyModuleImp(router) with HasRegMap
{
val io = bundleBuilder
val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
val io = IO(bundleBuilder)
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
}
@ -104,5 +102,5 @@ class AHBRegisterRouter[B <: AHBRegBundleBase, M <: LazyModuleImp]
require (isPow2(size))
// require (size >= 4096) ... not absolutely required, but highly recommended
lazy val module = moduleBuilder(bundleBuilder(AHBRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
lazy val module = moduleBuilder(bundleBuilder(AHBRegBundleArg()), this)
}

6
src/main/scala/amba/ahb/SRAM.scala
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@ -22,15 +22,11 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
require ((address.mask & (beatBytes-1)) == beatBytes-1)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
val mask = bigBits(address.mask >> log2Ceil(beatBytes))
val in = io.in(0)
val (in, _) = node.in(0)
// The mask and address during the address phase
val a_access = in.htrans === AHBParameters.TRANS_NONSEQ || in.htrans === AHBParameters.TRANS_SEQ

19
src/main/scala/amba/ahb/Test.scala
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@ -30,7 +30,7 @@ class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
ram.node := xbar.node
gpio.node := xbar.node
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
@ -42,7 +42,7 @@ class AHBNativeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(imp
class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
{
val node = AHBOutputNode()
val node = AHBIdentityNode()
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
@ -55,10 +55,9 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
model.node))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val out = node.bundleOut
val io = IO(new Bundle {
val finished = Bool(OUTPUT)
}
})
io.finished := fuzz.module.io.finished
}
@ -66,7 +65,7 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
{
val node = AHBInputNode()
val node = AHBIdentityNode()
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
ram.node :=
@ -77,11 +76,7 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
AHBToTL()(
node)))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
}
lazy val module = new LazyModuleImp(this) { }
}
class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
@ -91,7 +86,7 @@ class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
slave.node := master.node
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := master.module.io.finished
}
}

7
src/main/scala/amba/ahb/ToTL.scala
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@ -41,12 +41,7 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
val node = AHBToTLNode()
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val beatBytes = edgeOut.manager.beatBytes
val d_send = RegInit(Bool(false))

22
src/main/scala/amba/ahb/Xbar.scala
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@ -16,35 +16,31 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
// Require consistent bus widths
val port0 = node.edgesOut(0).slave
node.edgesOut.foreach { edge =>
val (io_out, edgesOut) = node.out.unzip
val port0 = edgesOut(0).slave
edgesOut.foreach { edge =>
val port = edge.slave
require (port.beatBytes == port0.beatBytes,
s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}")
}
val port_addrs = node.edgesOut.map(_.slave.slaves.map(_.address).flatten)
val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten)
val routingMask = AddressDecoder(port_addrs)
val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
val in = io.in(0)
val (in, _) = node.in(0)
val a_sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.haddr)).reduce(_ || _)))
val d_sel = Reg(a_sel)
when (in.hready) { d_sel := a_sel }
(a_sel zip io.out) foreach { case (sel, out) =>
(a_sel zip io_out) foreach { case (sel, out) =>
out := in
out.hsel := in.hsel && sel
}
in.hreadyout := !Mux1H(d_sel, io.out.map(!_.hreadyout))
in.hresp := Mux1H(d_sel, io.out.map(_.hresp))
in.hrdata := Mux1H(d_sel, io.out.map(_.hrdata))
in.hreadyout := !Mux1H(d_sel, io_out.map(!_.hreadyout))
in.hresp := Mux1H(d_sel, io_out.map(_.hresp))
in.hrdata := Mux1H(d_sel, io_out.map(_.hrdata))
}
}

17
src/main/scala/amba/apb/Nodes.scala
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@ -9,8 +9,8 @@ import freechips.rocketchip.diplomacy._
object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBEdgeParameters, APBBundle]
{
def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu)
def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu)
def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters): APBEdgeParameters = APBEdgeParameters(pd, pu, p)
def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters): APBEdgeParameters = APBEdgeParameters(pd, pu, p)
def bundleO(eo: APBEdgeParameters): APBBundle = APBBundle(eo.bundle)
def bundleI(ei: APBEdgeParameters): APBBundle = APBBundle(ei.bundle)
@ -25,8 +25,6 @@ object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, A
pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })
}
// Nodes implemented inside modules
case class APBIdentityNode()(implicit valName: ValName) extends IdentityNode(APBImp)
case class APBMasterNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends SourceNode(APBImp)(portParams)
case class APBSlaveNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends SinkNode(APBImp)(portParams)
case class APBNexusNode(
@ -37,13 +35,4 @@ case class APBNexusNode(
implicit valName: ValName)
extends NexusNode(APBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
// Nodes passed from an inner module
case class APBOutputNode()(implicit valName: ValName) extends OutputNode(APBImp)
case class APBInputNode()(implicit valName: ValName) extends InputNode(APBImp)
// Nodes used for external ports
case class APBBlindOutputNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(APBImp)(portParams)
case class APBBlindInputNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends BlindInputNode(APBImp)(portParams)
case class APBInternalOutputNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(APBImp)(portParams)
case class APBInternalInputNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends InternalInputNode(APBImp)(portParams)
case class APBIdentityNode()(implicit valName: ValName) extends IdentityNode(APBImp)()

3
src/main/scala/amba/apb/Parameters.scala
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@ -78,7 +78,8 @@ object APBBundleParameters
case class APBEdgeParameters(
master: APBMasterPortParameters,
slave: APBSlavePortParameters)
slave: APBSlavePortParameters,
params: Parameters)
{
val bundle = APBBundleParameters(master, slave)
}

12
src/main/scala/amba/apb/RegisterRouter.scala
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@ -24,7 +24,7 @@ case class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes:
// Calling this method causes the matching APB bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val apb = bundleIn(0)
val (apb, _) = this.in(0)
val indexBits = log2Up((address.mask+1)/beatBytes)
val params = RegMapperParams(indexBits, beatBytes, 1)
@ -60,13 +60,11 @@ abstract class APBRegisterRouterBase(address: AddressSet, interrupts: Int, concu
val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts))
}
case class APBRegBundleArg(interrupts: HeterogeneousBag[Vec[Bool]], in: HeterogeneousBag[APBBundle])(implicit val p: Parameters)
case class APBRegBundleArg()(implicit val p: Parameters)
class APBRegBundleBase(arg: APBRegBundleArg) extends Bundle
{
implicit val p = arg.p
val interrupts = arg.interrupts
val in = arg.in
}
class APBRegBundle[P](val params: P, arg: APBRegBundleArg) extends APBRegBundleBase(arg)
@ -74,8 +72,8 @@ class APBRegBundle[P](val params: P, arg: APBRegBundleArg) extends APBRegBundleB
class APBRegModule[P, B <: APBRegBundleBase](val params: P, bundleBuilder: => B, router: APBRegisterRouterBase)
extends LazyModuleImp(router) with HasRegMap
{
val io = bundleBuilder
val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
val io = IO(bundleBuilder)
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
}
@ -88,5 +86,5 @@ class APBRegisterRouter[B <: APBRegBundleBase, M <: LazyModuleImp]
require (isPow2(size))
// require (size >= 4096) ... not absolutely required, but highly recommended
lazy val module = moduleBuilder(bundleBuilder(APBRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
lazy val module = moduleBuilder(bundleBuilder(APBRegBundleArg()), this)
}

6
src/main/scala/amba/apb/SRAM.scala
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@ -22,11 +22,7 @@ class APBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
require ((address.mask & (beatBytes-1)) == beatBytes-1)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
val in = io.in(0)
val (in, _) = node.in(0)
def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)

2
src/main/scala/amba/apb/Test.scala
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@ -34,7 +34,7 @@ class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
TLDelayer(0.2)(
model.node))))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}

22
src/main/scala/amba/apb/Xbar.scala
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@ -16,34 +16,30 @@ class APBFanout()(implicit p: Parameters) extends LazyModule {
slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
val in = io.in(0)
val (in, _) = node.in(0)
// Require consistent bus widths
val port0 = node.edgesOut(0).slave
node.edgesOut.foreach { edge =>
val (io_out, edgesOut) = node.out.unzip
val port0 = edgesOut(0).slave
edgesOut.foreach { edge =>
val port = edge.slave
require (port.beatBytes == port0.beatBytes,
s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}")
}
val port_addrs = node.edgesOut.map(_.slave.slaves.map(_.address).flatten)
val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten)
val routingMask = AddressDecoder(port_addrs)
val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
val sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.paddr)).reduce(_ || _)))
(sel zip io.out) foreach { case (sel, out) =>
(sel zip io_out) foreach { case (sel, out) =>
out := in
out.psel := sel && in.psel
out.penable := sel && in.penable
}
in.pready := !Mux1H(sel, io.out.map(!_.pready))
in.pslverr := Mux1H(sel, io.out.map(_.pslverr))
in.prdata := Mux1H(sel, io.out.map(_.prdata))
in.pready := !Mux1H(sel, io_out.map(!_.pready))
in.pslverr := Mux1H(sel, io_out.map(_.pslverr))
in.prdata := Mux1H(sel, io_out.map(_.prdata))
}
}

7
src/main/scala/amba/axi4/Buffer.scala
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@ -26,11 +26,6 @@ class AXI4Buffer(
slaveFn = { p => p.copy(minLatency = p.minLatency + min(aw.latency,ar.latency) + min(r.latency,b.latency)) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
def buffer[T <: Data](config: BufferParams, data: IrrevocableIO[T]): IrrevocableIO[T] = {
if (config.isDefined) {
Queue.irrevocable(data, config.depth, pipe=config.pipe, flow=config.flow)
@ -39,7 +34,7 @@ class AXI4Buffer(
}
}
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.aw <> buffer(aw, in .aw)
out.w <> buffer(w, in .w)
in .b <> buffer(b, out.b)

7
src/main/scala/amba/axi4/Deinterleaver.scala
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@ -22,12 +22,7 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
})
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val endId = edgeOut.master.endId
val beatBytes = edgeOut.slave.beatBytes
val beats = (maxReadBytes+beatBytes-1) / beatBytes

7
src/main/scala/amba/axi4/Fragmenter.scala
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@ -26,12 +26,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
slaveFn = { sp => sp.copy(slaves = sp.slaves .map(s => mapSlave(s, sp.beatBytes))) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val slave = edgeOut.slave
val slaves = slave.slaves
val beatBytes = slave.beatBytes

7
src/main/scala/amba/axi4/IdIndexer.scala
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@ -42,12 +42,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
})
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// Leave everything mostly untouched
out.ar <> in.ar

18
src/main/scala/amba/axi4/Nodes.scala
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@ -9,8 +9,8 @@ import freechips.rocketchip.diplomacy._
object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle]
{
def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p)
def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p)
def bundleO(eo: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(eo.bundle)
def bundleI(ei: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(ei.bundle)
@ -25,8 +25,6 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters
pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })
}
// Nodes implemented inside modules
case class AXI4IdentityNode()(implicit valName: ValName) extends IdentityNode(AXI4Imp)
case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends SourceNode(AXI4Imp)(portParams)
case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends SinkNode(AXI4Imp)(portParams)
case class AXI4AdapterNode(
@ -35,14 +33,4 @@ case class AXI4AdapterNode(
numPorts: Range.Inclusive = 0 to 999)(
implicit valName: ValName)
extends AdapterNode(AXI4Imp)(masterFn, slaveFn, numPorts)
// Nodes passed from an inner module
case class AXI4OutputNode()(implicit valName: ValName) extends OutputNode(AXI4Imp)
case class AXI4InputNode()(implicit valName: ValName) extends InputNode(AXI4Imp)
// Nodes used for external ports
case class AXI4BlindOutputNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends BlindOutputNode(AXI4Imp)(portParams)
case class AXI4BlindInputNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends BlindInputNode(AXI4Imp)(portParams)
case class AXI4InternalOutputNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends InternalOutputNode(AXI4Imp)(portParams)
case class AXI4InternalInputNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends InternalInputNode(AXI4Imp)(portParams)
case class AXI4IdentityNode()(implicit valName: ValName) extends IdentityNode(AXI4Imp)()

3
src/main/scala/amba/axi4/Parameters.scala
View File

@ -124,7 +124,8 @@ object AXI4BundleParameters
case class AXI4EdgeParameters(
master: AXI4MasterPortParameters,
slave: AXI4SlavePortParameters)
slave: AXI4SlavePortParameters,
params: Parameters)
{
val bundle = AXI4BundleParameters(master, slave)
}

21
src/main/scala/amba/axi4/RegisterRouter.scala
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@ -26,11 +26,12 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes
// Calling this method causes the matching AXI4 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val ar = bundleIn(0).ar
val aw = bundleIn(0).aw
val w = bundleIn(0).w
val r = bundleIn(0).r
val b = bundleIn(0).b
val (io, _) = this.in(0)
val ar = io.ar
val aw = io.aw
val w = io.w
val r = io.r
val b = io.b
val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, ar.bits.params.idBits + ar.bits.params.userBits)
val in = Wire(Decoupled(new RegMapperInput(params)))
@ -86,13 +87,11 @@ abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, conc
val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts))
}
case class AXI4RegBundleArg(interrupts: HeterogeneousBag[Vec[Bool]], in: HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters)
case class AXI4RegBundleArg()(implicit val p: Parameters)
class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle
{
implicit val p = arg.p
val interrupts = arg.interrupts
val in = arg.in
}
class AXI4RegBundle[P](val params: P, arg: AXI4RegBundleArg) extends AXI4RegBundleBase(arg)
@ -100,8 +99,8 @@ class AXI4RegBundle[P](val params: P, arg: AXI4RegBundleArg) extends AXI4RegBund
class AXI4RegModule[P, B <: AXI4RegBundleBase](val params: P, bundleBuilder: => B, router: AXI4RegisterRouterBase)
extends LazyModuleImp(router) with HasRegMap
{
val io = bundleBuilder
val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
val io = IO(bundleBuilder)
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
}
@ -114,5 +113,5 @@ class AXI4RegisterRouter[B <: AXI4RegBundleBase, M <: LazyModuleImp]
require (isPow2(size))
// require (size >= 4096) ... not absolutely required, but highly recommended
lazy val module = moduleBuilder(bundleBuilder(AXI4RegBundleArg(intnode.bundleOut, node.bundleIn)), this)
lazy val module = moduleBuilder(bundleBuilder(AXI4RegBundleArg()), this)
}

6
src/main/scala/amba/axi4/SRAM.scala
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@ -24,15 +24,11 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
require ((address.mask & (beatBytes-1)) == beatBytes-1)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
val mask = bigBits(address.mask >> log2Ceil(beatBytes))
val in = io.in(0)
val (in, _) = node.in(0)
val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8)))
val r_addr = Cat((mask zip (in.ar.bits.addr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)

21
src/main/scala/amba/axi4/Test.scala
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@ -30,7 +30,7 @@ class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
ram.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(4, true )(TLFragmenter(4, 16)(xbar.node))))
gpio.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(4, false)(TLFragmenter(4, 16)(xbar.node))))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
@ -53,7 +53,7 @@ class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4,false)(xbar.node)))
gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4,true )(xbar.node)))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
@ -69,7 +69,7 @@ trait HasFuzzTarget {
class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget
{
val node = AXI4OutputNode()
val node = AXI4IdentityNode()
val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
@ -84,10 +84,9 @@ class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with
model.node))))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val out = node.bundleOut
val io = IO(new Bundle {
val finished = Bool(OUTPUT)
}
})
io.finished := fuzz.module.io.finished
}
@ -95,7 +94,7 @@ class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with
class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTarget
{
val node = AXI4InputNode()
val node = AXI4IdentityNode()
val xbar = LazyModule(new TLXbar)
val ram = LazyModule(new TLRAM(fuzzAddr))
val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256)))
@ -114,11 +113,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
AXI4IdIndexer(2)(
node))))))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}
}
lazy val module = new LazyModuleImp(this) { }
}
class AXI4FuzzBridge(txns: Int)(implicit p: Parameters) extends LazyModule
@ -128,7 +123,7 @@ class AXI4FuzzBridge(txns: Int)(implicit p: Parameters) extends LazyModule
slave.node := master.node
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := master.module.io.finished
}
}

7
src/main/scala/amba/axi4/ToTL.scala
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@ -44,12 +44,7 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
val node = AXI4ToTLNode()
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.manager.beatBytes
val beatCountBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1

7
src/main/scala/amba/axi4/UserYanker.scala
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@ -22,12 +22,7 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
slaveFn = { sp => sp })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val bits = edgeIn.bundle.userBits
val need_bypass = edgeOut.slave.minLatency < 1
require (bits > 0) // useless UserYanker!