riscv/rocket-chip
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Use HeaderlessTileLinkIO

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This commit is contained in:
Henry Cook
2015-03-26 23:26:03 -07:00
parent 24bb032ede
commit 91e882e3f8
5 changed files with 45 additions and 102 deletions
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rocket/src/main/scala/tile.scala
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@ -44,7 +44,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
// otherwise, just hookup the icache
io.uncached <> params(BuildRoCC).map { buildItHere =>
val rocc = buildItHere()
val memArb = Module(new RocketUncachedTileLinkIOArbiter(3))
val memArb = Module(new HeaderlessTileLinkIOArbiter(3))
val dcIF = Module(new SimpleHellaCacheIF)
core.io.rocc <> rocc.io
dcIF.io.requestor <> rocc.io.mem