clean up the requirements in StatelessBridge
* No need to check that release ID bits and acquire ID bits the same * Check that inner and outer coherence policies match
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@ -31,22 +31,20 @@ import cde.{Parameters, Field, Config}
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*/
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*/
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class ManagerToClientStatelessBridge(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
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class ManagerToClientStatelessBridge(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
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val icid = io.inner.tlClientIdBits
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val ixid = io.inner.tlClientXactIdBits
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val oxid = io.outer.tlClientXactIdBits
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val icid = io.inner.acquire.bits.client_id.getWidth
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val innerCoh = io.inner.tlCoh.getClass
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val ixid = io.inner.acquire.bits.client_xact_id.getWidth
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val outerCoh = io.outer.tlCoh.getClass
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val oxid = io.outer.acquire.bits.client_xact_id.getWidth
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// Stateless Bridge is only usable in certain constrained situations.
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// Stateless Bridge is only usable in certain constrained situations.
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// Sanity check its usage here.
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// Sanity check its usage here.
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// Additional requirements are that the inner and outer Coherence policies
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// are the same (e.g. MEI != MESI), and that NTiles == 1,
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// but this is not checked here.
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require (p(NTiles) == 1)
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require(io.inner.tlNCachingClients <= 1)
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require(icid + ixid <= oxid)
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require(icid + ixid <= oxid)
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require(icid == io.inner.release.bits.client_id.getWidth)
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require(innerCoh eq outerCoh,
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require(ixid == io.inner.release.bits.client_xact_id.getWidth)
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s"Coherence policies do not match: inner is ${innerCoh.getSimpleName}, outer is ${outerCoh.getSimpleName}")
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require(oxid == io.outer.release.bits.client_xact_id.getWidth)
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io.outer.acquire.valid := io.inner.acquire.valid
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io.outer.acquire.valid := io.inner.acquire.valid
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io.inner.acquire.ready := io.outer.acquire.ready
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io.inner.acquire.ready := io.outer.acquire.ready
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