From 915697cb0903280667f7f10b2eb61787f63a9472 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <aswaterman@gmail.com>
Date: Tue, 6 Dec 2016 11:54:29 -0800
Subject: [PATCH] Fix FEQ flag generation (#479)

FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).

Also, minor code cleanup.
---
 src/main/scala/rocket/fpu.scala | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/rocket/fpu.scala b/src/main/scala/rocket/fpu.scala
index a29f12d3..ce5c6a21 100644
--- a/src/main/scala/rocket/fpu.scala
+++ b/src/main/scala/rocket/fpu.scala
@@ -308,17 +308,15 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
   val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
   dcmp.io.a := in.in1
   dcmp.io.b := in.in2
-  dcmp.io.signaling := Bool(true)
-  val dcmp_out = (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR
-  val dcmp_exc = dcmp.io.exceptionFlags
+  dcmp.io.signaling := !in.rm(1)
 
   io.out.bits.toint := Mux(in.rm(0), classify_out, unrec_int)
   io.out.bits.store := unrec_mem
   io.out.bits.exc := Bits(0)
 
   when (in.cmd === FCMD_CMP) {
-    io.out.bits.toint := dcmp_out
-    io.out.bits.exc := dcmp_exc
+    io.out.bits.toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR
+    io.out.bits.exc := dcmp.io.exceptionFlags
   }
   when (in.cmd === FCMD_CVT_IF) {
     val minXLen = 32