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assmebly tests are now built from riscv-tests

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Yunsup Lee 2013-04-24 01:59:14 -07:00
parent 93df795e48
commit 9114012def
3 changed files with 484 additions and 484 deletions
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@ -16,484 +16,483 @@ libdramsim.a: $(DRAMSIM_OBJS)
# Tests
#--------------------------------------------------------------------
# Globally installed assembly tests
global_tstdir = $(basedir)/riscv-asmtests-bmarks/riscv-tests
global_asm_tests = \
riscv_ipi \
riscv_lrsc \
riscv_add \
riscv_addi \
riscv_amoadd_d \
riscv_amoadd_w \
riscv_amoand_d \
riscv_amoand_w \
riscv_amoor_d \
riscv_amoor_w \
riscv_amoswap_d \
riscv_amoswap_w \
riscv_amomax_d \
riscv_amomax_w \
riscv_amomaxu_d \
riscv_amomaxu_w \
riscv_amomin_d \
riscv_amomin_w \
riscv_amominu_d \
riscv_amominu_w \
riscv_fence_i \
riscv_sb \
riscv_sd \
riscv_sh \
riscv_sw \
riscv_addiw \
riscv_addw \
riscv_and \
riscv_andi \
riscv_beq \
riscv_bge \
riscv_bgeu \
riscv_blt \
riscv_bltu \
riscv_bne \
riscv_div \
riscv_divu \
riscv_divuw \
riscv_divw \
riscv_j \
riscv_jal \
riscv_jalr \
riscv_jalr_j \
riscv_jalr_r \
riscv_lb \
riscv_lbu \
riscv_ld \
riscv_lh \
riscv_lhu \
riscv_lui \
riscv_lw \
riscv_lwu \
riscv_mul \
riscv_mulh \
riscv_mulhsu \
riscv_mulhu \
riscv_mulw \
riscv_or \
riscv_ori \
riscv_auipc \
riscv_rem \
riscv_remu \
riscv_remuw \
riscv_remw \
riscv_simple \
riscv_sll \
riscv_slli \
riscv_slliw \
riscv_sllw \
riscv_slt \
riscv_slti \
riscv_sltiu \
riscv_sltu \
riscv_sra \
riscv_srai \
riscv_sraiw \
riscv_sraw \
riscv_srliw \
riscv_srlw \
riscv_sub \
riscv_subw \
riscv_xor \
riscv_xori \
riscv_fp_ldst \
riscv_fp_move \
riscv_fsgnj \
riscv_fcmp \
riscv_fcvt \
riscv_fcvt_w \
riscv_fadd \
riscv_fmin \
riscv_fmadd \
riscv_fp_structural \
tstdir = $(basedir)/riscv-tests/isa
asm_p_tests = \
rv64si-pm-ipi \
rv64ui-pm-lrsc \
rv64ui-p-add \
rv64ui-p-addi \
rv64ui-p-amoadd_d \
rv64ui-p-amoadd_w \
rv64ui-p-amoand_d \
rv64ui-p-amoand_w \
rv64ui-p-amoor_d \
rv64ui-p-amoor_w \
rv64ui-p-amoswap_d \
rv64ui-p-amoswap_w \
rv64ui-p-amomax_d \
rv64ui-p-amomax_w \
rv64ui-p-amomaxu_d \
rv64ui-p-amomaxu_w \
rv64ui-p-amomin_d \
rv64ui-p-amomin_w \
rv64ui-p-amominu_d \
rv64ui-p-amominu_w \
rv64ui-p-auipc \
rv64ui-p-fence_i \
rv64ui-p-sb \
rv64ui-p-sd \
rv64ui-p-sh \
rv64ui-p-sw \
rv64ui-p-addiw \
rv64ui-p-addw \
rv64ui-p-and \
rv64ui-p-andi \
rv64ui-p-beq \
rv64ui-p-bge \
rv64ui-p-bgeu \
rv64ui-p-blt \
rv64ui-p-bltu \
rv64ui-p-bne \
rv64ui-p-div \
rv64ui-p-divu \
rv64ui-p-divuw \
rv64ui-p-divw \
rv64ui-p-j \
rv64ui-p-jal \
rv64ui-p-jalr \
rv64ui-p-jalr_j \
rv64ui-p-jalr_r \
rv64ui-p-lb \
rv64ui-p-lbu \
rv64ui-p-ld \
rv64ui-p-lh \
rv64ui-p-lhu \
rv64ui-p-lui \
rv64ui-p-lw \
rv64ui-p-lwu \
rv64ui-p-mul \
rv64ui-p-mulh \
rv64ui-p-mulhsu \
rv64ui-p-mulhu \
rv64ui-p-mulw \
rv64ui-p-or \
rv64ui-p-ori \
rv64ui-p-rem \
rv64ui-p-remu \
rv64ui-p-remuw \
rv64ui-p-remw \
rv64ui-p-simple \
rv64ui-p-sll \
rv64ui-p-slli \
rv64ui-p-slliw \
rv64ui-p-sllw \
rv64ui-p-slt \
rv64ui-p-slti \
rv64ui-p-sltiu \
rv64ui-p-sltu \
rv64ui-p-sra \
rv64ui-p-srai \
rv64ui-p-sraiw \
rv64ui-p-sraw \
rv64ui-p-srliw \
rv64ui-p-srlw \
rv64ui-p-sub \
rv64ui-p-subw \
rv64ui-p-xor \
rv64ui-p-xori \
rv64uf-p-ldst \
rv64uf-p-move \
rv64uf-p-fsgnj \
rv64uf-p-fcmp \
rv64uf-p-fcvt \
rv64uf-p-fcvt_w \
rv64uf-p-fadd \
rv64uf-p-fmin \
rv64uf-p-fmadd \
rv64uf-p-structural \
global_asm_vm_tests = \
riscv_add_vm \
riscv_addi_vm \
riscv_amoadd_d_vm \
riscv_amoadd_w_vm \
riscv_amoand_d_vm \
riscv_amoand_w_vm \
riscv_amoor_d_vm \
riscv_amoor_w_vm \
riscv_amoswap_d_vm \
riscv_amoswap_w_vm \
riscv_amomax_d_vm \
riscv_amomax_w_vm \
riscv_amomaxu_d_vm \
riscv_amomaxu_w_vm \
riscv_amomin_d_vm \
riscv_amomin_w_vm \
riscv_amominu_d_vm \
riscv_amominu_w_vm \
riscv_fence_i_vm \
riscv_sb_vm \
riscv_sd_vm \
riscv_sh_vm \
riscv_sw_vm \
riscv_addiw_vm \
riscv_addw_vm \
riscv_and_vm \
riscv_andi_vm \
riscv_beq_vm \
riscv_bge_vm \
riscv_bgeu_vm \
riscv_blt_vm \
riscv_bltu_vm \
riscv_bne_vm \
riscv_div_vm \
riscv_divu_vm \
riscv_divuw_vm \
riscv_divw_vm \
riscv_j_vm \
riscv_jal_vm \
riscv_jalr_vm \
riscv_jalr_j_vm \
riscv_jalr_r_vm \
riscv_lb_vm \
riscv_lbu_vm \
riscv_ld_vm \
riscv_lh_vm \
riscv_lhu_vm \
riscv_lui_vm \
riscv_lw_vm \
riscv_lwu_vm \
riscv_mul_vm \
riscv_mulh_vm \
riscv_mulhsu_vm \
riscv_mulhu_vm \
riscv_mulw_vm \
riscv_or_vm \
riscv_ori_vm \
riscv_rdnpc_vm \
riscv_rem_vm \
riscv_remu_vm \
riscv_remuw_vm \
riscv_remw_vm \
riscv_sll_vm \
riscv_slli_vm \
riscv_slliw_vm \
riscv_sllw_vm \
riscv_slt_vm \
riscv_slti_vm \
riscv_sltiu_vm \
riscv_sltu_vm \
riscv_sra_vm \
riscv_srai_vm \
riscv_sraiw_vm \
riscv_sraw_vm \
riscv_srliw_vm \
riscv_srlw_vm \
riscv_sub_vm \
riscv_subw_vm \
riscv_xor_vm \
riscv_xori_vm \
riscv_fp_ldst_vm \
riscv_fp_move_vm \
riscv_fsgnj_vm \
riscv_fcmp_vm \
riscv_fcvt_vm \
riscv_fcvt_w_vm \
riscv_fadd_vm \
riscv_fmin_vm \
riscv_fmadd_vm \
riscv_fp_structural_vm \
asm_v_tests = \
rv64ui-v-add \
rv64ui-v-addi \
rv64ui-v-amoadd_d \
rv64ui-v-amoadd_w \
rv64ui-v-amoand_d \
rv64ui-v-amoand_w \
rv64ui-v-amoor_d \
rv64ui-v-amoor_w \
rv64ui-v-amoswap_d \
rv64ui-v-amoswap_w \
rv64ui-v-amomax_d \
rv64ui-v-amomax_w \
rv64ui-v-amomaxu_d \
rv64ui-v-amomaxu_w \
rv64ui-v-amomin_d \
rv64ui-v-amomin_w \
rv64ui-v-amominu_d \
rv64ui-v-amominu_w \
rv64ui-v-auipc \
rv64ui-v-fence_i \
rv64ui-v-sb \
rv64ui-v-sd \
rv64ui-v-sh \
rv64ui-v-sw \
rv64ui-v-addiw \
rv64ui-v-addw \
rv64ui-v-and \
rv64ui-v-andi \
rv64ui-v-beq \
rv64ui-v-bge \
rv64ui-v-bgeu \
rv64ui-v-blt \
rv64ui-v-bltu \
rv64ui-v-bne \
rv64ui-v-div \
rv64ui-v-divu \
rv64ui-v-divuw \
rv64ui-v-divw \
rv64ui-v-j \
rv64ui-v-jal \
rv64ui-v-jalr \
rv64ui-v-jalr_j \
rv64ui-v-jalr_r \
rv64ui-v-lb \
rv64ui-v-lbu \
rv64ui-v-ld \
rv64ui-v-lh \
rv64ui-v-lhu \
rv64ui-v-lui \
rv64ui-v-lw \
rv64ui-v-lwu \
rv64ui-v-mul \
rv64ui-v-mulh \
rv64ui-v-mulhsu \
rv64ui-v-mulhu \
rv64ui-v-mulw \
rv64ui-v-or \
rv64ui-v-ori \
rv64ui-v-rem \
rv64ui-v-remu \
rv64ui-v-remuw \
rv64ui-v-remw \
rv64ui-v-sll \
rv64ui-v-slli \
rv64ui-v-slliw \
rv64ui-v-sllw \
rv64ui-v-slt \
rv64ui-v-slti \
rv64ui-v-sltiu \
rv64ui-v-sltu \
rv64ui-v-sra \
rv64ui-v-srai \
rv64ui-v-sraiw \
rv64ui-v-sraw \
rv64ui-v-srliw \
rv64ui-v-srlw \
rv64ui-v-sub \
rv64ui-v-subw \
rv64ui-v-xor \
rv64ui-v-xori \
rv64uf-v-ldst \
rv64uf-v-move \
rv64uf-v-fsgnj \
rv64uf-v-fcmp \
rv64uf-v-fcvt \
rv64uf-v-fcvt_w \
rv64uf-v-fadd \
rv64uf-v-fmin \
rv64uf-v-fmadd \
rv64uf-v-structural \
global_vecasm_tests = \
riscv_vec_wakeup_vec \
riscv_vec_fence_vec \
riscv_vec_utidx_vec \
riscv_vec_vmsv_vec \
riscv_vec_vmvv_vec \
riscv_vec_vfmvv_vec \
riscv_vec_movz_vec \
riscv_vec_movn_vec \
riscv_vec_fmovz_vec \
riscv_vec_fmovn_vec \
riscv_vec_ld_vec \
riscv_vec_lw_vec \
riscv_vec_lwu_vec \
riscv_vec_lh_vec \
riscv_vec_lhu_vec \
riscv_vec_lb_vec \
riscv_vec_lbu_vec \
riscv_vec_sd_vec \
riscv_vec_sw_vec \
riscv_vec_sh_vec \
riscv_vec_sb_vec \
riscv_vec_fld_vec \
riscv_vec_flw_vec \
riscv_vec_fsd_vec \
riscv_vec_fsw_vec \
riscv_vec_fcvt-d-l_vec \
riscv_vec_vvadd_d_vec \
riscv_vec_vvadd_fw_vec \
riscv_vec_vvadd_fd_vec \
riscv_vec_vvadd_w_vec \
riscv_vec_vvmul_d_vec \
riscv_vec_amoadd_d_vec \
riscv_vec_amoswap_d_vec \
riscv_vec_amoand_d_vec \
riscv_vec_amoor_d_vec \
riscv_vec_amomax_d_vec \
riscv_vec_amomin_d_vec \
riscv_vec_amomaxu_d_vec \
riscv_vec_amominu_d_vec \
riscv_vec_amoadd_w_vec \
riscv_vec_amoswap_w_vec \
riscv_vec_amoand_w_vec \
riscv_vec_amoor_w_vec \
riscv_vec_amomax_w_vec \
riscv_vec_amomin_w_vec \
riscv_vec_amomaxu_w_vec \
riscv_vec_amominu_w_vec \
riscv_vec_imul_vec \
riscv_vec_fma_vec \
riscv_mul_vec \
riscv_mulw_vec \
riscv_mulh_vec \
riscv_mulhu_vec \
riscv_mulhsu_vec \
riscv_addi_vec \
riscv_add_vec \
riscv_addiw_vec \
riscv_addw_vec \
riscv_and_vec \
riscv_andi_vec \
riscv_lui_vec \
riscv_or_vec \
riscv_ori_vec \
riscv_slt_vec \
riscv_sltu_vec \
riscv_slti_vec \
riscv_sltiu_vec \
riscv_slli_vec \
riscv_sll_vec \
riscv_slliw_vec \
riscv_sllw_vec \
riscv_srai_vec \
riscv_sra_vec \
riscv_sraiw_vec \
riscv_sraw_vec \
riscv_srli_vec \
riscv_srl_vec \
riscv_srliw_vec \
riscv_srlw_vec \
riscv_sub_vec \
riscv_subw_vec \
riscv_xor_vec \
riscv_xori_vec \
riscv_fadd_vec \
riscv_fsgnj_vec \
riscv_fmin_vec \
riscv_fmadd_vec \
riscv_fcvt_w_vec \
riscv_fcvt_vec \
riscv_fcmp_vec \
riscv_vec_xcpt_ma_inst \
riscv_vec_xcpt_illegal \
riscv_vec_xcpt_illegal_vt_regid \
riscv_vec_xcpt_illegal_tvec_regid \
riscv_vec_ma_vld \
riscv_vec_ma_vsd \
riscv_vec_ma_utld \
riscv_vec_ma_utsd \
riscv_vec_illegal_tvec \
vecasm_p_tests = \
rv64uv-p-wakeup \
rv64uv-p-fence \
rv64uv-p-utidx \
rv64uv-p-vmsv \
rv64uv-p-vmvv \
rv64uv-p-vfmvv \
rv64uv-p-movz \
rv64uv-p-movn \
rv64uv-p-fmovz \
rv64uv-p-fmovn \
rv64uv-p-ld \
rv64uv-p-lw \
rv64uv-p-lwu \
rv64uv-p-lh \
rv64uv-p-lhu \
rv64uv-p-lb \
rv64uv-p-lbu \
rv64uv-p-sd \
rv64uv-p-sw \
rv64uv-p-sh \
rv64uv-p-sb \
rv64uv-p-fld \
rv64uv-p-flw \
rv64uv-p-fsd \
rv64uv-p-fsw \
rv64uv-p-fcvt \
rv64uv-p-vvadd_d \
rv64uv-p-vvadd_fw \
rv64uv-p-vvadd_fd \
rv64uv-p-vvadd_w \
rv64uv-p-vvmul_d \
rv64uv-p-amoadd_d \
rv64uv-p-amoswap_d \
rv64uv-p-amoand_d \
rv64uv-p-amoor_d \
rv64uv-p-amomax_d \
rv64uv-p-amomin_d \
rv64uv-p-amomaxu_d \
rv64uv-p-amominu_d \
rv64uv-p-amoadd_w \
rv64uv-p-amoswap_w \
rv64uv-p-amoand_w \
rv64uv-p-amoor_w \
rv64uv-p-amomax_w \
rv64uv-p-amomin_w \
rv64uv-p-amomaxu_w \
rv64uv-p-amominu_w \
rv64uv-p-imul \
rv64uv-p-fma \
rv64ui-p-vec-mul \
rv64ui-p-vec-mulw \
rv64ui-p-vec-mulh \
rv64ui-p-vec-mulhu \
rv64ui-p-vec-mulhsu \
rv64ui-p-vec-addi \
rv64ui-p-vec-add \
rv64ui-p-vec-addiw \
rv64ui-p-vec-addw \
rv64ui-p-vec-and \
rv64ui-p-vec-andi \
rv64ui-p-vec-lui \
rv64ui-p-vec-or \
rv64ui-p-vec-ori \
rv64ui-p-vec-slt \
rv64ui-p-vec-sltu \
rv64ui-p-vec-slti \
rv64ui-p-vec-sltiu \
rv64ui-p-vec-slli \
rv64ui-p-vec-sll \
rv64ui-p-vec-slliw \
rv64ui-p-vec-sllw \
rv64ui-p-vec-srai \
rv64ui-p-vec-sra \
rv64ui-p-vec-sraiw \
rv64ui-p-vec-sraw \
rv64ui-p-vec-srli \
rv64ui-p-vec-srl \
rv64ui-p-vec-srliw \
rv64ui-p-vec-srlw \
rv64ui-p-vec-sub \
rv64ui-p-vec-subw \
rv64ui-p-vec-xor \
rv64ui-p-vec-xori \
rv64uf-p-vec-fadd \
rv64uf-p-vec-fsgnj \
rv64uf-p-vec-fmin \
rv64uf-p-vec-fmadd \
rv64uf-p-vec-fcvt_w \
rv64uf-p-vec-fcvt \
rv64uf-p-vec-fcmp \
rv64sv-p-illegal_tvec_cmd \
rv64sv-p-illegal_tvec_regid \
rv64sv-p-illegal_vt_inst \
rv64sv-p-illegal_vt_regid \
rv64sv-p-ma_utld \
rv64sv-p-ma_utsd \
rv64sv-p-ma_vld \
rv64sv-p-ma_vsd \
rv64sv-p-ma_vt_inst \
global_vecasm_vm_tests = \
riscv_vec_wakeup_vec_vm \
riscv_vec_fence_vec_vm \
riscv_vec_utidx_vec_vm \
riscv_vec_vmsv_vec_vm \
riscv_vec_vmvv_vec_vm \
riscv_vec_vfmvv_vec_vm \
riscv_vec_movz_vec_vm \
riscv_vec_movn_vec_vm \
riscv_vec_fmovz_vec_vm \
riscv_vec_fmovn_vec_vm \
riscv_vec_ld_vec_vm \
riscv_vec_lw_vec_vm \
riscv_vec_lwu_vec_vm \
riscv_vec_lh_vec_vm \
riscv_vec_lhu_vec_vm \
riscv_vec_lb_vec_vm \
riscv_vec_lbu_vec_vm \
riscv_vec_sd_vec_vm \
riscv_vec_sw_vec_vm \
riscv_vec_sh_vec_vm \
riscv_vec_sb_vec_vm \
riscv_vec_fld_vec_vm \
riscv_vec_flw_vec_vm \
riscv_vec_fsd_vec_vm \
riscv_vec_fsw_vec_vm \
riscv_vec_fcvt-d-l_vec_vm \
riscv_vec_vvadd_d_vec_vm \
riscv_vec_vvadd_fw_vec_vm \
riscv_vec_vvadd_fd_vec_vm \
riscv_vec_vvadd_w_vec_vm \
riscv_vec_vvmul_d_vec_vm \
riscv_vec_amoadd_d_vec_vm \
riscv_vec_amoswap_d_vec_vm \
riscv_vec_amoand_d_vec_vm \
riscv_vec_amoor_d_vec_vm \
riscv_vec_amomax_d_vec_vm \
riscv_vec_amomin_d_vec_vm \
riscv_vec_amomaxu_d_vec_vm \
riscv_vec_amominu_d_vec_vm \
riscv_vec_amoadd_w_vec_vm \
riscv_vec_amoswap_w_vec_vm \
riscv_vec_amoand_w_vec_vm \
riscv_vec_amoor_w_vec_vm \
riscv_vec_amomax_w_vec_vm \
riscv_vec_amomin_w_vec_vm \
riscv_vec_amomaxu_w_vec_vm \
riscv_vec_amominu_w_vec_vm \
riscv_vec_imul_vec_vm \
riscv_vec_fma_vec_vm \
riscv_mul_vec_vm \
riscv_mulw_vec_vm \
riscv_mulh_vec_vm \
riscv_mulhu_vec_vm \
riscv_mulhsu_vec_vm \
riscv_addi_vec_vm \
riscv_add_vec_vm \
riscv_addiw_vec_vm \
riscv_addw_vec_vm \
riscv_and_vec_vm \
riscv_andi_vec_vm \
riscv_lui_vec_vm \
riscv_or_vec_vm \
riscv_ori_vec_vm \
riscv_slt_vec_vm \
riscv_sltu_vec_vm \
riscv_slti_vec_vm \
riscv_sltiu_vec_vm \
riscv_slli_vec_vm \
riscv_sll_vec_vm \
riscv_slliw_vec_vm \
riscv_sllw_vec_vm \
riscv_srai_vec_vm \
riscv_sra_vec_vm \
riscv_sraiw_vec_vm \
riscv_sraw_vec_vm \
riscv_srli_vec_vm \
riscv_srl_vec_vm \
riscv_srliw_vec_vm \
riscv_srlw_vec_vm \
riscv_sub_vec_vm \
riscv_subw_vec_vm \
riscv_xor_vec_vm \
riscv_xori_vec_vm \
riscv_fadd_vec_vm \
riscv_fsgnj_vec_vm \
riscv_fmin_vec_vm \
riscv_fmadd_vec_vm \
riscv_fcvt_w_vec_vm \
riscv_fcvt_vec_vm \
riscv_fcmp_vec_vm \
vecasm_v_tests = \
rv64uv-v-wakeup \
rv64uv-v-fence \
rv64uv-v-utidx \
rv64uv-v-vmsv \
rv64uv-v-vmvv \
rv64uv-v-vfmvv \
rv64uv-v-movz \
rv64uv-v-movn \
rv64uv-v-fmovz \
rv64uv-v-fmovn \
rv64uv-v-ld \
rv64uv-v-lw \
rv64uv-v-lwu \
rv64uv-v-lh \
rv64uv-v-lhu \
rv64uv-v-lb \
rv64uv-v-lbu \
rv64uv-v-sd \
rv64uv-v-sw \
rv64uv-v-sh \
rv64uv-v-sb \
rv64uv-v-fld \
rv64uv-v-flw \
rv64uv-v-fsd \
rv64uv-v-fsw \
rv64uv-v-fcvt \
rv64uv-v-vvadd_d \
rv64uv-v-vvadd_fw \
rv64uv-v-vvadd_fd \
rv64uv-v-vvadd_w \
rv64uv-v-vvmul_d \
rv64uv-v-amoadd_d \
rv64uv-v-amoswap_d \
rv64uv-v-amoand_d \
rv64uv-v-amoor_d \
rv64uv-v-amomax_d \
rv64uv-v-amomin_d \
rv64uv-v-amomaxu_d \
rv64uv-v-amominu_d \
rv64uv-v-amoadd_w \
rv64uv-v-amoswap_w \
rv64uv-v-amoand_w \
rv64uv-v-amoor_w \
rv64uv-v-amomax_w \
rv64uv-v-amomin_w \
rv64uv-v-amomaxu_w \
rv64uv-v-amominu_w \
rv64uv-v-imul \
rv64uv-v-fma \
rv64ui-v-vec-mul \
rv64ui-v-vec-mulw \
rv64ui-v-vec-mulh \
rv64ui-v-vec-mulhu \
rv64ui-v-vec-mulhsu \
rv64ui-v-vec-addi \
rv64ui-v-vec-add \
rv64ui-v-vec-addiw \
rv64ui-v-vec-addw \
rv64ui-v-vec-and \
rv64ui-v-vec-andi \
rv64ui-v-vec-lui \
rv64ui-v-vec-or \
rv64ui-v-vec-ori \
rv64ui-v-vec-slt \
rv64ui-v-vec-sltu \
rv64ui-v-vec-slti \
rv64ui-v-vec-sltiu \
rv64ui-v-vec-slli \
rv64ui-v-vec-sll \
rv64ui-v-vec-slliw \
rv64ui-v-vec-sllw \
rv64ui-v-vec-srai \
rv64ui-v-vec-sra \
rv64ui-v-vec-sraiw \
rv64ui-v-vec-sraw \
rv64ui-v-vec-srli \
rv64ui-v-vec-srl \
rv64ui-v-vec-srliw \
rv64ui-v-vec-srlw \
rv64ui-v-vec-sub \
rv64ui-v-vec-subw \
rv64ui-v-vec-xor \
rv64ui-v-vec-xori \
rv64uf-v-vec-fadd \
rv64uf-v-vec-fsgnj \
rv64uf-v-vec-fmin \
rv64uf-v-vec-fmadd \
rv64uf-v-vec-fcvt_w \
rv64uf-v-vec-fcvt \
rv64uf-v-vec-fcmp \
global_vecasm_timer_tests = \
riscv_vec_wakeup_vec_timer \
riscv_vec_fence_vec_timer \
riscv_vec_vvadd_d_vec_timer \
riscv_vec_vvadd_fw_vec_timer \
riscv_vec_vvadd_fd_vec_timer \
riscv_vec_vvadd_w_vec_timer \
riscv_vec_vvmul_d_vec_timer \
riscv_vec_fcvt-d-l_vec_timer \
riscv_vec_utidx_vec_timer \
riscv_vec_vmvv_vec_timer \
riscv_vec_vmsv_vec_timer \
riscv_vec_vfmvv_vec_timer \
riscv_vec_movz_vec_timer \
riscv_vec_movn_vec_timer \
riscv_vec_fmovz_vec_timer \
riscv_vec_fmovn_vec_timer \
riscv_vec_ld_vec_timer \
riscv_vec_lw_vec_timer \
riscv_vec_lwu_vec_timer \
riscv_vec_lh_vec_timer \
riscv_vec_lhu_vec_timer \
riscv_vec_lb_vec_timer \
riscv_vec_lbu_vec_timer \
riscv_vec_sd_vec_timer \
riscv_vec_sw_vec_timer \
riscv_vec_sh_vec_timer \
riscv_vec_sb_vec_timer \
riscv_vec_fld_vec_timer \
riscv_vec_flw_vec_timer \
riscv_vec_fsd_vec_timer \
riscv_vec_fsw_vec_timer \
riscv_vec_amoadd_d_vec_timer \
riscv_vec_amoswap_d_vec_timer \
riscv_vec_amoand_d_vec_timer \
riscv_vec_amoor_d_vec_timer \
riscv_vec_amomax_d_vec_timer \
riscv_vec_amomin_d_vec_timer \
riscv_vec_amomaxu_d_vec_timer \
riscv_vec_amominu_d_vec_timer \
riscv_vec_amoadd_w_vec_timer \
riscv_vec_amoswap_w_vec_timer \
riscv_vec_amoand_w_vec_timer \
riscv_vec_amoor_w_vec_timer \
riscv_vec_amomax_w_vec_timer \
riscv_vec_amomin_w_vec_timer \
riscv_vec_amomaxu_w_vec_timer \
riscv_vec_amominu_w_vec_timer \
riscv_vec_imul_vec_timer \
riscv_vec_fma_vec_timer \
riscv_mul_vec_timer \
riscv_mulw_vec_timer \
riscv_mulh_vec_timer \
riscv_mulhu_vec_timer \
riscv_mulhsu_vec_timer \
riscv_addi_vec_timer \
riscv_add_vec_timer \
riscv_addiw_vec_timer \
riscv_addw_vec_timer \
riscv_and_vec_timer \
riscv_andi_vec_timer \
riscv_lui_vec_timer \
riscv_or_vec_timer \
riscv_ori_vec_timer \
riscv_slt_vec_timer \
riscv_sltu_vec_timer \
riscv_slti_vec_timer \
riscv_sltiu_vec_timer \
riscv_slli_vec_timer \
riscv_sll_vec_timer \
riscv_slliw_vec_timer \
riscv_sllw_vec_timer \
riscv_srai_vec_timer \
riscv_sra_vec_timer \
riscv_sraiw_vec_timer \
riscv_sraw_vec_timer \
riscv_srli_vec_timer \
riscv_srl_vec_timer \
riscv_srliw_vec_timer \
riscv_srlw_vec_timer \
riscv_sub_vec_timer \
riscv_subw_vec_timer \
riscv_xor_vec_timer \
riscv_xori_vec_timer \
riscv_fadd_vec_timer \
riscv_fsgnj_vec_timer \
riscv_fmin_vec_timer \
riscv_fmadd_vec_timer \
riscv_fcvt_w_vec_timer \
riscv_fcvt_vec_timer \
riscv_fcmp_vec_timer \
vecasm_pt_tests = \
rv64uv-pt-wakeup \
rv64uv-pt-fence \
rv64uv-pt-vvadd_d \
rv64uv-pt-vvadd_fw \
rv64uv-pt-vvadd_fd \
rv64uv-pt-vvadd_w \
rv64uv-pt-vvmul_d \
rv64uv-pt-fcvt \
rv64uv-pt-utidx \
rv64uv-pt-vmvv \
rv64uv-pt-vmsv \
rv64uv-pt-vfmvv \
rv64uv-pt-movz \
rv64uv-pt-movn \
rv64uv-pt-fmovz \
rv64uv-pt-fmovn \
rv64uv-pt-ld \
rv64uv-pt-lw \
rv64uv-pt-lwu \
rv64uv-pt-lh \
rv64uv-pt-lhu \
rv64uv-pt-lb \
rv64uv-pt-lbu \
rv64uv-pt-sd \
rv64uv-pt-sw \
rv64uv-pt-sh \
rv64uv-pt-sb \
rv64uv-pt-fld \
rv64uv-pt-flw \
rv64uv-pt-fsd \
rv64uv-pt-fsw \
rv64uv-pt-amoadd_d \
rv64uv-pt-amoswap_d \
rv64uv-pt-amoand_d \
rv64uv-pt-amoor_d \
rv64uv-pt-amomax_d \
rv64uv-pt-amomin_d \
rv64uv-pt-amomaxu_d \
rv64uv-pt-amominu_d \
rv64uv-pt-amoadd_w \
rv64uv-pt-amoswap_w \
rv64uv-pt-amoand_w \
rv64uv-pt-amoor_w \
rv64uv-pt-amomax_w \
rv64uv-pt-amomin_w \
rv64uv-pt-amomaxu_w \
rv64uv-pt-amominu_w \
rv64uv-pt-imul \
rv64uv-pt-fma \
rv64ui-pt-vec-mul \
rv64ui-pt-vec-mulw \
rv64ui-pt-vec-mulh \
rv64ui-pt-vec-mulhu \
rv64ui-pt-vec-mulhsu \
rv64ui-pt-vec-addi \
rv64ui-pt-vec-add \
rv64ui-pt-vec-addiw \
rv64ui-pt-vec-addw \
rv64ui-pt-vec-and \
rv64ui-pt-vec-andi \
rv64ui-pt-vec-lui \
rv64ui-pt-vec-or \
rv64ui-pt-vec-ori \
rv64ui-pt-vec-slt \
rv64ui-pt-vec-sltu \
rv64ui-pt-vec-slti \
rv64ui-pt-vec-sltiu \
rv64ui-pt-vec-slli \
rv64ui-pt-vec-sll \
rv64ui-pt-vec-slliw \
rv64ui-pt-vec-sllw \
rv64ui-pt-vec-srai \
rv64ui-pt-vec-sra \
rv64ui-pt-vec-sraiw \
rv64ui-pt-vec-sraw \
rv64ui-pt-vec-srli \
rv64ui-pt-vec-srl \
rv64ui-pt-vec-srliw \
rv64ui-pt-vec-srlw \
rv64ui-pt-vec-sub \
rv64ui-pt-vec-subw \
rv64ui-pt-vec-xor \
rv64ui-pt-vec-xori \
rv64uf-pt-vec-fadd \
rv64uf-pt-vec-fsgnj \
rv64uf-pt-vec-fmin \
rv64uf-pt-vec-fmadd \
rv64uf-pt-vec-fcvt_w \
rv64uf-pt-vec-fcvt \
rv64uf-pt-vec-fcmp \
# Globally installed benchmarks
global_bmarkdir = $(basedir)/riscv-asmtests-bmarks/riscv-bmarks
global_bmarks = \
bmarkdir = $(basedir)/riscv-asmtests-bmarks/riscv-bmarks
bmarks = \
median.riscv \
multiply.riscv \
qsort.riscv \
@ -506,8 +505,8 @@ global_bmarks = \
vec_cmplxmult.riscv \
vec_matmul.riscv \
global_vec_bmarkdir = $(basedir)/../../riscv-app/misc/build
global_vec_bmarks = \
vec_bmarkdir = $(basedir)/../../riscv-app/misc/build
vec_bmarks = \
ubmark-vvadd \
ubmark-bin-search \
ubmark-cmplx-mult \

22
emulator/Makefile
View File

@ -56,11 +56,11 @@ test:
%.riscv.hex: %
$(MAKE) -C $(dir $@) $(notdir $@)
$(addprefix output/, $(addsuffix .hex, $(global_asm_tests) $(global_asm_vm_tests) $(global_vecasm_tests) $(global_vecasm_vm_tests) $(global_vecasm_timer_tests))): output/%.hex: $(global_tstdir)/%.hex
$(addprefix output/, $(addsuffix .hex, $(asm_p_tests) $(asm_v_tests) $(vecasm_p_tests) $(vecasm_v_tests) $(vecasm_pt_tests))): output/%.hex: $(tstdir)/%.hex
mkdir -p output
ln -fs ../$< $@
$(addprefix output/, $(addsuffix .hex, $(global_bmarks))): output/%.hex: $(global_bmarkdir)/%.hex
$(addprefix output/, $(addsuffix .hex, $(bmarks))): output/%.hex: $(bmarkdir)/%.hex
mkdir -p output
ln -fs ../$< $@
@ -78,24 +78,24 @@ output/%.vpd: output/%.hex emulator-debug
vcd2vpd $@.vcd $@ > /dev/null &
./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@)
run-asm-tests: $(addprefix output/, $(addsuffix .out, $(global_asm_tests) $(global_asm_vm_tests)))
run-asm-tests: $(addprefix output/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
run-vecasm-tests: $(addprefix output/, $(addsuffix .out, $(global_vecasm_tests) $(global_vecasm_vm_tests)))
run-vecasm-tests: $(addprefix output/, $(addsuffix .out, $(vecasm_p_tests) $(vecasm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
run-vecasm-timer-tests: $(addprefix output/, $(addsuffix .out, $(global_vecasm_timer_tests)))
run-vecasm-timer-tests: $(addprefix output/, $(addsuffix .out, $(vecasm_pt_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
run-bmarks-test: $(addprefix output/, $(addsuffix .out, $(global_bmarks)))
run-bmarks-test: $(addprefix output/, $(addsuffix .out, $(bmarks)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
run-asm-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(global_asm_tests) $(global_asm_vm_tests)))
run-asm-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(asm_p_tests) $(asm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run-vecasm-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(global_vecasm_tests) $(global_vecasm_vm_tests)))
run-vecasm-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(vecasm_p_tests) $(vecasm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run-vecasm-timer-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(global_vecasm_timer_tests)))
run-vecasm-timer-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(vecasm_pt_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run-bmarks-test-debug: $(addprefix output/, $(addsuffix .vpd, $(global_bmarks)))
run-bmarks-test-debug: $(addprefix output/, $(addsuffix .vpd, $(bmarks)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run: run-asm-tests run-vecasm-tests run-vecasm-timer-tests run-bmarks-test
run-debug: run-asm-tests-debug run-vecasm-tests-debug run-vecasm-timer-tests-debug run-bmarks-test-debug
run-fast: $(addprefix output/, $(addsuffix .run, $(global_asm_tests) $(global_asm_vm_tests) $(global_bmarks)))
run-fast: $(addprefix output/, $(addsuffix .run, $(asm_p_tests) $(asm_v_tests) $(bmarks)))

1
riscv-tests Submodule

@ -0,0 +1 @@
Subproject commit f8ea498f79ab4d6495f2966d1e5c3dd42f567752