riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

assmebly tests are now built from riscv-tests

Browse Source
This commit is contained in:
Yunsup Lee 2013-04-24 01:59:14 -07:00
parent 93df795e48
commit 9114012def
3 changed files with 484 additions and 484 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

945
Makefrag
View File

@ -16,484 +16,483 @@ libdramsim.a: $(DRAMSIM_OBJS)
# Tests # Tests
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Globally installed assembly tests tstdir = $(basedir)/riscv-tests/isa
global_tstdir = $(basedir)/riscv-asmtests-bmarks/riscv-tests asm_p_tests = \
global_asm_tests = \ rv64si-pm-ipi \
riscv_ipi \ rv64ui-pm-lrsc \
riscv_lrsc \ rv64ui-p-add \
riscv_add \ rv64ui-p-addi \
riscv_addi \ rv64ui-p-amoadd_d \
riscv_amoadd_d \ rv64ui-p-amoadd_w \
riscv_amoadd_w \ rv64ui-p-amoand_d \
riscv_amoand_d \ rv64ui-p-amoand_w \
riscv_amoand_w \ rv64ui-p-amoor_d \
riscv_amoor_d \ rv64ui-p-amoor_w \
riscv_amoor_w \ rv64ui-p-amoswap_d \
riscv_amoswap_d \ rv64ui-p-amoswap_w \
riscv_amoswap_w \ rv64ui-p-amomax_d \
riscv_amomax_d \ rv64ui-p-amomax_w \
riscv_amomax_w \ rv64ui-p-amomaxu_d \
riscv_amomaxu_d \ rv64ui-p-amomaxu_w \
riscv_amomaxu_w \ rv64ui-p-amomin_d \
riscv_amomin_d \ rv64ui-p-amomin_w \
riscv_amomin_w \ rv64ui-p-amominu_d \
riscv_amominu_d \ rv64ui-p-amominu_w \
riscv_amominu_w \ rv64ui-p-auipc \
riscv_fence_i \ rv64ui-p-fence_i \
riscv_sb \ rv64ui-p-sb \
riscv_sd \ rv64ui-p-sd \
riscv_sh \ rv64ui-p-sh \
riscv_sw \ rv64ui-p-sw \
riscv_addiw \ rv64ui-p-addiw \
riscv_addw \ rv64ui-p-addw \
riscv_and \ rv64ui-p-and \
riscv_andi \ rv64ui-p-andi \
riscv_beq \ rv64ui-p-beq \
riscv_bge \ rv64ui-p-bge \
riscv_bgeu \ rv64ui-p-bgeu \
riscv_blt \ rv64ui-p-blt \
riscv_bltu \ rv64ui-p-bltu \
riscv_bne \ rv64ui-p-bne \
riscv_div \ rv64ui-p-div \
riscv_divu \ rv64ui-p-divu \
riscv_divuw \ rv64ui-p-divuw \
riscv_divw \ rv64ui-p-divw \
riscv_j \ rv64ui-p-j \
riscv_jal \ rv64ui-p-jal \
riscv_jalr \ rv64ui-p-jalr \
riscv_jalr_j \ rv64ui-p-jalr_j \
riscv_jalr_r \ rv64ui-p-jalr_r \
riscv_lb \ rv64ui-p-lb \
riscv_lbu \ rv64ui-p-lbu \
riscv_ld \ rv64ui-p-ld \
riscv_lh \ rv64ui-p-lh \
riscv_lhu \ rv64ui-p-lhu \
riscv_lui \ rv64ui-p-lui \
riscv_lw \ rv64ui-p-lw \
riscv_lwu \ rv64ui-p-lwu \
riscv_mul \ rv64ui-p-mul \
riscv_mulh \ rv64ui-p-mulh \
riscv_mulhsu \ rv64ui-p-mulhsu \
riscv_mulhu \ rv64ui-p-mulhu \
riscv_mulw \ rv64ui-p-mulw \
riscv_or \ rv64ui-p-or \
riscv_ori \ rv64ui-p-ori \
riscv_auipc \ rv64ui-p-rem \
riscv_rem \ rv64ui-p-remu \
riscv_remu \ rv64ui-p-remuw \
riscv_remuw \ rv64ui-p-remw \
riscv_remw \ rv64ui-p-simple \
riscv_simple \ rv64ui-p-sll \
riscv_sll \ rv64ui-p-slli \
riscv_slli \ rv64ui-p-slliw \
riscv_slliw \ rv64ui-p-sllw \
riscv_sllw \ rv64ui-p-slt \
riscv_slt \ rv64ui-p-slti \
riscv_slti \ rv64ui-p-sltiu \
riscv_sltiu \ rv64ui-p-sltu \
riscv_sltu \ rv64ui-p-sra \
riscv_sra \ rv64ui-p-srai \
riscv_srai \ rv64ui-p-sraiw \
riscv_sraiw \ rv64ui-p-sraw \
riscv_sraw \ rv64ui-p-srliw \
riscv_srliw \ rv64ui-p-srlw \
riscv_srlw \ rv64ui-p-sub \
riscv_sub \ rv64ui-p-subw \
riscv_subw \ rv64ui-p-xor \
riscv_xor \ rv64ui-p-xori \
riscv_xori \ rv64uf-p-ldst \
riscv_fp_ldst \ rv64uf-p-move \
riscv_fp_move \ rv64uf-p-fsgnj \
riscv_fsgnj \ rv64uf-p-fcmp \
riscv_fcmp \ rv64uf-p-fcvt \
riscv_fcvt \ rv64uf-p-fcvt_w \
riscv_fcvt_w \ rv64uf-p-fadd \
riscv_fadd \ rv64uf-p-fmin \
riscv_fmin \ rv64uf-p-fmadd \
riscv_fmadd \ rv64uf-p-structural \
riscv_fp_structural \
global_asm_vm_tests = \ asm_v_tests = \
riscv_add_vm \ rv64ui-v-add \
riscv_addi_vm \ rv64ui-v-addi \
riscv_amoadd_d_vm \ rv64ui-v-amoadd_d \
riscv_amoadd_w_vm \ rv64ui-v-amoadd_w \
riscv_amoand_d_vm \ rv64ui-v-amoand_d \
riscv_amoand_w_vm \ rv64ui-v-amoand_w \
riscv_amoor_d_vm \ rv64ui-v-amoor_d \
riscv_amoor_w_vm \ rv64ui-v-amoor_w \
riscv_amoswap_d_vm \ rv64ui-v-amoswap_d \
riscv_amoswap_w_vm \ rv64ui-v-amoswap_w \
riscv_amomax_d_vm \ rv64ui-v-amomax_d \
riscv_amomax_w_vm \ rv64ui-v-amomax_w \
riscv_amomaxu_d_vm \ rv64ui-v-amomaxu_d \
riscv_amomaxu_w_vm \ rv64ui-v-amomaxu_w \
riscv_amomin_d_vm \ rv64ui-v-amomin_d \
riscv_amomin_w_vm \ rv64ui-v-amomin_w \
riscv_amominu_d_vm \ rv64ui-v-amominu_d \
riscv_amominu_w_vm \ rv64ui-v-amominu_w \
riscv_fence_i_vm \ rv64ui-v-auipc \
riscv_sb_vm \ rv64ui-v-fence_i \
riscv_sd_vm \ rv64ui-v-sb \
riscv_sh_vm \ rv64ui-v-sd \
riscv_sw_vm \ rv64ui-v-sh \
riscv_addiw_vm \ rv64ui-v-sw \
riscv_addw_vm \ rv64ui-v-addiw \
riscv_and_vm \ rv64ui-v-addw \
riscv_andi_vm \ rv64ui-v-and \
riscv_beq_vm \ rv64ui-v-andi \
riscv_bge_vm \ rv64ui-v-beq \
riscv_bgeu_vm \ rv64ui-v-bge \
riscv_blt_vm \ rv64ui-v-bgeu \
riscv_bltu_vm \ rv64ui-v-blt \
riscv_bne_vm \ rv64ui-v-bltu \
riscv_div_vm \ rv64ui-v-bne \
riscv_divu_vm \ rv64ui-v-div \
riscv_divuw_vm \ rv64ui-v-divu \
riscv_divw_vm \ rv64ui-v-divuw \
riscv_j_vm \ rv64ui-v-divw \
riscv_jal_vm \ rv64ui-v-j \
riscv_jalr_vm \ rv64ui-v-jal \
riscv_jalr_j_vm \ rv64ui-v-jalr \
riscv_jalr_r_vm \ rv64ui-v-jalr_j \
riscv_lb_vm \ rv64ui-v-jalr_r \
riscv_lbu_vm \ rv64ui-v-lb \
riscv_ld_vm \ rv64ui-v-lbu \
riscv_lh_vm \ rv64ui-v-ld \
riscv_lhu_vm \ rv64ui-v-lh \
riscv_lui_vm \ rv64ui-v-lhu \
riscv_lw_vm \ rv64ui-v-lui \
riscv_lwu_vm \ rv64ui-v-lw \
riscv_mul_vm \ rv64ui-v-lwu \
riscv_mulh_vm \ rv64ui-v-mul \
riscv_mulhsu_vm \ rv64ui-v-mulh \
riscv_mulhu_vm \ rv64ui-v-mulhsu \
riscv_mulw_vm \ rv64ui-v-mulhu \
riscv_or_vm \ rv64ui-v-mulw \
riscv_ori_vm \ rv64ui-v-or \
riscv_rdnpc_vm \ rv64ui-v-ori \
riscv_rem_vm \ rv64ui-v-rem \
riscv_remu_vm \ rv64ui-v-remu \
riscv_remuw_vm \ rv64ui-v-remuw \
riscv_remw_vm \ rv64ui-v-remw \
riscv_sll_vm \ rv64ui-v-sll \
riscv_slli_vm \ rv64ui-v-slli \
riscv_slliw_vm \ rv64ui-v-slliw \
riscv_sllw_vm \ rv64ui-v-sllw \
riscv_slt_vm \ rv64ui-v-slt \
riscv_slti_vm \ rv64ui-v-slti \
riscv_sltiu_vm \ rv64ui-v-sltiu \
riscv_sltu_vm \ rv64ui-v-sltu \
riscv_sra_vm \ rv64ui-v-sra \
riscv_srai_vm \ rv64ui-v-srai \
riscv_sraiw_vm \ rv64ui-v-sraiw \
riscv_sraw_vm \ rv64ui-v-sraw \
riscv_srliw_vm \ rv64ui-v-srliw \
riscv_srlw_vm \ rv64ui-v-srlw \
riscv_sub_vm \ rv64ui-v-sub \
riscv_subw_vm \ rv64ui-v-subw \
riscv_xor_vm \ rv64ui-v-xor \
riscv_xori_vm \ rv64ui-v-xori \
riscv_fp_ldst_vm \ rv64uf-v-ldst \
riscv_fp_move_vm \ rv64uf-v-move \
riscv_fsgnj_vm \ rv64uf-v-fsgnj \
riscv_fcmp_vm \ rv64uf-v-fcmp \
riscv_fcvt_vm \ rv64uf-v-fcvt \
riscv_fcvt_w_vm \ rv64uf-v-fcvt_w \
riscv_fadd_vm \ rv64uf-v-fadd \
riscv_fmin_vm \ rv64uf-v-fmin \
riscv_fmadd_vm \ rv64uf-v-fmadd \
riscv_fp_structural_vm \ rv64uf-v-structural \
global_vecasm_tests = \ vecasm_p_tests = \
riscv_vec_wakeup_vec \ rv64uv-p-wakeup \
riscv_vec_fence_vec \ rv64uv-p-fence \
riscv_vec_utidx_vec \ rv64uv-p-utidx \
riscv_vec_vmsv_vec \ rv64uv-p-vmsv \
riscv_vec_vmvv_vec \ rv64uv-p-vmvv \
riscv_vec_vfmvv_vec \ rv64uv-p-vfmvv \
riscv_vec_movz_vec \ rv64uv-p-movz \
riscv_vec_movn_vec \ rv64uv-p-movn \
riscv_vec_fmovz_vec \ rv64uv-p-fmovz \
riscv_vec_fmovn_vec \ rv64uv-p-fmovn \
riscv_vec_ld_vec \ rv64uv-p-ld \
riscv_vec_lw_vec \ rv64uv-p-lw \
riscv_vec_lwu_vec \ rv64uv-p-lwu \
riscv_vec_lh_vec \ rv64uv-p-lh \
riscv_vec_lhu_vec \ rv64uv-p-lhu \
riscv_vec_lb_vec \ rv64uv-p-lb \
riscv_vec_lbu_vec \ rv64uv-p-lbu \
riscv_vec_sd_vec \ rv64uv-p-sd \
riscv_vec_sw_vec \ rv64uv-p-sw \
riscv_vec_sh_vec \ rv64uv-p-sh \
riscv_vec_sb_vec \ rv64uv-p-sb \
riscv_vec_fld_vec \ rv64uv-p-fld \
riscv_vec_flw_vec \ rv64uv-p-flw \
riscv_vec_fsd_vec \ rv64uv-p-fsd \
riscv_vec_fsw_vec \ rv64uv-p-fsw \
riscv_vec_fcvt-d-l_vec \ rv64uv-p-fcvt \
riscv_vec_vvadd_d_vec \ rv64uv-p-vvadd_d \
riscv_vec_vvadd_fw_vec \ rv64uv-p-vvadd_fw \
riscv_vec_vvadd_fd_vec \ rv64uv-p-vvadd_fd \
riscv_vec_vvadd_w_vec \ rv64uv-p-vvadd_w \
riscv_vec_vvmul_d_vec \ rv64uv-p-vvmul_d \
riscv_vec_amoadd_d_vec \ rv64uv-p-amoadd_d \
riscv_vec_amoswap_d_vec \ rv64uv-p-amoswap_d \
riscv_vec_amoand_d_vec \ rv64uv-p-amoand_d \
riscv_vec_amoor_d_vec \ rv64uv-p-amoor_d \
riscv_vec_amomax_d_vec \ rv64uv-p-amomax_d \
riscv_vec_amomin_d_vec \ rv64uv-p-amomin_d \
riscv_vec_amomaxu_d_vec \ rv64uv-p-amomaxu_d \
riscv_vec_amominu_d_vec \ rv64uv-p-amominu_d \
riscv_vec_amoadd_w_vec \ rv64uv-p-amoadd_w \
riscv_vec_amoswap_w_vec \ rv64uv-p-amoswap_w \
riscv_vec_amoand_w_vec \ rv64uv-p-amoand_w \
riscv_vec_amoor_w_vec \ rv64uv-p-amoor_w \
riscv_vec_amomax_w_vec \ rv64uv-p-amomax_w \
riscv_vec_amomin_w_vec \ rv64uv-p-amomin_w \
riscv_vec_amomaxu_w_vec \ rv64uv-p-amomaxu_w \
riscv_vec_amominu_w_vec \ rv64uv-p-amominu_w \
riscv_vec_imul_vec \ rv64uv-p-imul \
riscv_vec_fma_vec \ rv64uv-p-fma \
riscv_mul_vec \ rv64ui-p-vec-mul \
riscv_mulw_vec \ rv64ui-p-vec-mulw \
riscv_mulh_vec \ rv64ui-p-vec-mulh \
riscv_mulhu_vec \ rv64ui-p-vec-mulhu \
riscv_mulhsu_vec \ rv64ui-p-vec-mulhsu \
riscv_addi_vec \ rv64ui-p-vec-addi \
riscv_add_vec \ rv64ui-p-vec-add \
riscv_addiw_vec \ rv64ui-p-vec-addiw \
riscv_addw_vec \ rv64ui-p-vec-addw \
riscv_and_vec \ rv64ui-p-vec-and \
riscv_andi_vec \ rv64ui-p-vec-andi \
riscv_lui_vec \ rv64ui-p-vec-lui \
riscv_or_vec \ rv64ui-p-vec-or \
riscv_ori_vec \ rv64ui-p-vec-ori \
riscv_slt_vec \ rv64ui-p-vec-slt \
riscv_sltu_vec \ rv64ui-p-vec-sltu \
riscv_slti_vec \ rv64ui-p-vec-slti \
riscv_sltiu_vec \ rv64ui-p-vec-sltiu \
riscv_slli_vec \ rv64ui-p-vec-slli \
riscv_sll_vec \ rv64ui-p-vec-sll \
riscv_slliw_vec \ rv64ui-p-vec-slliw \
riscv_sllw_vec \ rv64ui-p-vec-sllw \
riscv_srai_vec \ rv64ui-p-vec-srai \
riscv_sra_vec \ rv64ui-p-vec-sra \
riscv_sraiw_vec \ rv64ui-p-vec-sraiw \
riscv_sraw_vec \ rv64ui-p-vec-sraw \
riscv_srli_vec \ rv64ui-p-vec-srli \
riscv_srl_vec \ rv64ui-p-vec-srl \
riscv_srliw_vec \ rv64ui-p-vec-srliw \
riscv_srlw_vec \ rv64ui-p-vec-srlw \
riscv_sub_vec \ rv64ui-p-vec-sub \
riscv_subw_vec \ rv64ui-p-vec-subw \
riscv_xor_vec \ rv64ui-p-vec-xor \
riscv_xori_vec \ rv64ui-p-vec-xori \
riscv_fadd_vec \ rv64uf-p-vec-fadd \
riscv_fsgnj_vec \ rv64uf-p-vec-fsgnj \
riscv_fmin_vec \ rv64uf-p-vec-fmin \
riscv_fmadd_vec \ rv64uf-p-vec-fmadd \
riscv_fcvt_w_vec \ rv64uf-p-vec-fcvt_w \
riscv_fcvt_vec \ rv64uf-p-vec-fcvt \
riscv_fcmp_vec \ rv64uf-p-vec-fcmp \
riscv_vec_xcpt_ma_inst \ rv64sv-p-illegal_tvec_cmd \
riscv_vec_xcpt_illegal \ rv64sv-p-illegal_tvec_regid \
riscv_vec_xcpt_illegal_vt_regid \ rv64sv-p-illegal_vt_inst \
riscv_vec_xcpt_illegal_tvec_regid \ rv64sv-p-illegal_vt_regid \
riscv_vec_ma_vld \ rv64sv-p-ma_utld \
riscv_vec_ma_vsd \ rv64sv-p-ma_utsd \
riscv_vec_ma_utld \ rv64sv-p-ma_vld \
riscv_vec_ma_utsd \ rv64sv-p-ma_vsd \
riscv_vec_illegal_tvec \ rv64sv-p-ma_vt_inst \
global_vecasm_vm_tests = \ vecasm_v_tests = \
riscv_vec_wakeup_vec_vm \ rv64uv-v-wakeup \
riscv_vec_fence_vec_vm \ rv64uv-v-fence \
riscv_vec_utidx_vec_vm \ rv64uv-v-utidx \
riscv_vec_vmsv_vec_vm \ rv64uv-v-vmsv \
riscv_vec_vmvv_vec_vm \ rv64uv-v-vmvv \
riscv_vec_vfmvv_vec_vm \ rv64uv-v-vfmvv \
riscv_vec_movz_vec_vm \ rv64uv-v-movz \
riscv_vec_movn_vec_vm \ rv64uv-v-movn \
riscv_vec_fmovz_vec_vm \ rv64uv-v-fmovz \
riscv_vec_fmovn_vec_vm \ rv64uv-v-fmovn \
riscv_vec_ld_vec_vm \ rv64uv-v-ld \
riscv_vec_lw_vec_vm \ rv64uv-v-lw \
riscv_vec_lwu_vec_vm \ rv64uv-v-lwu \
riscv_vec_lh_vec_vm \ rv64uv-v-lh \
riscv_vec_lhu_vec_vm \ rv64uv-v-lhu \
riscv_vec_lb_vec_vm \ rv64uv-v-lb \
riscv_vec_lbu_vec_vm \ rv64uv-v-lbu \
riscv_vec_sd_vec_vm \ rv64uv-v-sd \
riscv_vec_sw_vec_vm \ rv64uv-v-sw \
riscv_vec_sh_vec_vm \ rv64uv-v-sh \
riscv_vec_sb_vec_vm \ rv64uv-v-sb \
riscv_vec_fld_vec_vm \ rv64uv-v-fld \
riscv_vec_flw_vec_vm \ rv64uv-v-flw \
riscv_vec_fsd_vec_vm \ rv64uv-v-fsd \
riscv_vec_fsw_vec_vm \ rv64uv-v-fsw \
riscv_vec_fcvt-d-l_vec_vm \ rv64uv-v-fcvt \
riscv_vec_vvadd_d_vec_vm \ rv64uv-v-vvadd_d \
riscv_vec_vvadd_fw_vec_vm \ rv64uv-v-vvadd_fw \
riscv_vec_vvadd_fd_vec_vm \ rv64uv-v-vvadd_fd \
riscv_vec_vvadd_w_vec_vm \ rv64uv-v-vvadd_w \
riscv_vec_vvmul_d_vec_vm \ rv64uv-v-vvmul_d \
riscv_vec_amoadd_d_vec_vm \ rv64uv-v-amoadd_d \
riscv_vec_amoswap_d_vec_vm \ rv64uv-v-amoswap_d \
riscv_vec_amoand_d_vec_vm \ rv64uv-v-amoand_d \
riscv_vec_amoor_d_vec_vm \ rv64uv-v-amoor_d \
riscv_vec_amomax_d_vec_vm \ rv64uv-v-amomax_d \
riscv_vec_amomin_d_vec_vm \ rv64uv-v-amomin_d \
riscv_vec_amomaxu_d_vec_vm \ rv64uv-v-amomaxu_d \
riscv_vec_amominu_d_vec_vm \ rv64uv-v-amominu_d \
riscv_vec_amoadd_w_vec_vm \ rv64uv-v-amoadd_w \
riscv_vec_amoswap_w_vec_vm \ rv64uv-v-amoswap_w \
riscv_vec_amoand_w_vec_vm \ rv64uv-v-amoand_w \
riscv_vec_amoor_w_vec_vm \ rv64uv-v-amoor_w \
riscv_vec_amomax_w_vec_vm \ rv64uv-v-amomax_w \
riscv_vec_amomin_w_vec_vm \ rv64uv-v-amomin_w \
riscv_vec_amomaxu_w_vec_vm \ rv64uv-v-amomaxu_w \
riscv_vec_amominu_w_vec_vm \ rv64uv-v-amominu_w \
riscv_vec_imul_vec_vm \ rv64uv-v-imul \
riscv_vec_fma_vec_vm \ rv64uv-v-fma \
riscv_mul_vec_vm \ rv64ui-v-vec-mul \
riscv_mulw_vec_vm \ rv64ui-v-vec-mulw \
riscv_mulh_vec_vm \ rv64ui-v-vec-mulh \
riscv_mulhu_vec_vm \ rv64ui-v-vec-mulhu \
riscv_mulhsu_vec_vm \ rv64ui-v-vec-mulhsu \
riscv_addi_vec_vm \ rv64ui-v-vec-addi \
riscv_add_vec_vm \ rv64ui-v-vec-add \
riscv_addiw_vec_vm \ rv64ui-v-vec-addiw \
riscv_addw_vec_vm \ rv64ui-v-vec-addw \
riscv_and_vec_vm \ rv64ui-v-vec-and \
riscv_andi_vec_vm \ rv64ui-v-vec-andi \
riscv_lui_vec_vm \ rv64ui-v-vec-lui \
riscv_or_vec_vm \ rv64ui-v-vec-or \
riscv_ori_vec_vm \ rv64ui-v-vec-ori \
riscv_slt_vec_vm \ rv64ui-v-vec-slt \
riscv_sltu_vec_vm \ rv64ui-v-vec-sltu \
riscv_slti_vec_vm \ rv64ui-v-vec-slti \
riscv_sltiu_vec_vm \ rv64ui-v-vec-sltiu \
riscv_slli_vec_vm \ rv64ui-v-vec-slli \
riscv_sll_vec_vm \ rv64ui-v-vec-sll \
riscv_slliw_vec_vm \ rv64ui-v-vec-slliw \
riscv_sllw_vec_vm \ rv64ui-v-vec-sllw \
riscv_srai_vec_vm \ rv64ui-v-vec-srai \
riscv_sra_vec_vm \ rv64ui-v-vec-sra \
riscv_sraiw_vec_vm \ rv64ui-v-vec-sraiw \
riscv_sraw_vec_vm \ rv64ui-v-vec-sraw \
riscv_srli_vec_vm \ rv64ui-v-vec-srli \
riscv_srl_vec_vm \ rv64ui-v-vec-srl \
riscv_srliw_vec_vm \ rv64ui-v-vec-srliw \
riscv_srlw_vec_vm \ rv64ui-v-vec-srlw \
riscv_sub_vec_vm \ rv64ui-v-vec-sub \
riscv_subw_vec_vm \ rv64ui-v-vec-subw \
riscv_xor_vec_vm \ rv64ui-v-vec-xor \
riscv_xori_vec_vm \ rv64ui-v-vec-xori \
riscv_fadd_vec_vm \ rv64uf-v-vec-fadd \
riscv_fsgnj_vec_vm \ rv64uf-v-vec-fsgnj \
riscv_fmin_vec_vm \ rv64uf-v-vec-fmin \
riscv_fmadd_vec_vm \ rv64uf-v-vec-fmadd \
riscv_fcvt_w_vec_vm \ rv64uf-v-vec-fcvt_w \
riscv_fcvt_vec_vm \ rv64uf-v-vec-fcvt \
riscv_fcmp_vec_vm \ rv64uf-v-vec-fcmp \
global_vecasm_timer_tests = \ vecasm_pt_tests = \
riscv_vec_wakeup_vec_timer \ rv64uv-pt-wakeup \
riscv_vec_fence_vec_timer \ rv64uv-pt-fence \
riscv_vec_vvadd_d_vec_timer \ rv64uv-pt-vvadd_d \
riscv_vec_vvadd_fw_vec_timer \ rv64uv-pt-vvadd_fw \
riscv_vec_vvadd_fd_vec_timer \ rv64uv-pt-vvadd_fd \
riscv_vec_vvadd_w_vec_timer \ rv64uv-pt-vvadd_w \
riscv_vec_vvmul_d_vec_timer \ rv64uv-pt-vvmul_d \
riscv_vec_fcvt-d-l_vec_timer \ rv64uv-pt-fcvt \
riscv_vec_utidx_vec_timer \ rv64uv-pt-utidx \
riscv_vec_vmvv_vec_timer \ rv64uv-pt-vmvv \
riscv_vec_vmsv_vec_timer \ rv64uv-pt-vmsv \
riscv_vec_vfmvv_vec_timer \ rv64uv-pt-vfmvv \
riscv_vec_movz_vec_timer \ rv64uv-pt-movz \
riscv_vec_movn_vec_timer \ rv64uv-pt-movn \
riscv_vec_fmovz_vec_timer \ rv64uv-pt-fmovz \
riscv_vec_fmovn_vec_timer \ rv64uv-pt-fmovn \
riscv_vec_ld_vec_timer \ rv64uv-pt-ld \
riscv_vec_lw_vec_timer \ rv64uv-pt-lw \
riscv_vec_lwu_vec_timer \ rv64uv-pt-lwu \
riscv_vec_lh_vec_timer \ rv64uv-pt-lh \
riscv_vec_lhu_vec_timer \ rv64uv-pt-lhu \
riscv_vec_lb_vec_timer \ rv64uv-pt-lb \
riscv_vec_lbu_vec_timer \ rv64uv-pt-lbu \
riscv_vec_sd_vec_timer \ rv64uv-pt-sd \
riscv_vec_sw_vec_timer \ rv64uv-pt-sw \
riscv_vec_sh_vec_timer \ rv64uv-pt-sh \
riscv_vec_sb_vec_timer \ rv64uv-pt-sb \
riscv_vec_fld_vec_timer \ rv64uv-pt-fld \
riscv_vec_flw_vec_timer \ rv64uv-pt-flw \
riscv_vec_fsd_vec_timer \ rv64uv-pt-fsd \
riscv_vec_fsw_vec_timer \ rv64uv-pt-fsw \
riscv_vec_amoadd_d_vec_timer \ rv64uv-pt-amoadd_d \
riscv_vec_amoswap_d_vec_timer \ rv64uv-pt-amoswap_d \
riscv_vec_amoand_d_vec_timer \ rv64uv-pt-amoand_d \
riscv_vec_amoor_d_vec_timer \ rv64uv-pt-amoor_d \
riscv_vec_amomax_d_vec_timer \ rv64uv-pt-amomax_d \
riscv_vec_amomin_d_vec_timer \ rv64uv-pt-amomin_d \
riscv_vec_amomaxu_d_vec_timer \ rv64uv-pt-amomaxu_d \
riscv_vec_amominu_d_vec_timer \ rv64uv-pt-amominu_d \
riscv_vec_amoadd_w_vec_timer \ rv64uv-pt-amoadd_w \
riscv_vec_amoswap_w_vec_timer \ rv64uv-pt-amoswap_w \
riscv_vec_amoand_w_vec_timer \ rv64uv-pt-amoand_w \
riscv_vec_amoor_w_vec_timer \ rv64uv-pt-amoor_w \
riscv_vec_amomax_w_vec_timer \ rv64uv-pt-amomax_w \
riscv_vec_amomin_w_vec_timer \ rv64uv-pt-amomin_w \
riscv_vec_amomaxu_w_vec_timer \ rv64uv-pt-amomaxu_w \
riscv_vec_amominu_w_vec_timer \ rv64uv-pt-amominu_w \
riscv_vec_imul_vec_timer \ rv64uv-pt-imul \
riscv_vec_fma_vec_timer \ rv64uv-pt-fma \
riscv_mul_vec_timer \ rv64ui-pt-vec-mul \
riscv_mulw_vec_timer \ rv64ui-pt-vec-mulw \
riscv_mulh_vec_timer \ rv64ui-pt-vec-mulh \
riscv_mulhu_vec_timer \ rv64ui-pt-vec-mulhu \
riscv_mulhsu_vec_timer \ rv64ui-pt-vec-mulhsu \
riscv_addi_vec_timer \ rv64ui-pt-vec-addi \
riscv_add_vec_timer \ rv64ui-pt-vec-add \
riscv_addiw_vec_timer \ rv64ui-pt-vec-addiw \
riscv_addw_vec_timer \ rv64ui-pt-vec-addw \
riscv_and_vec_timer \ rv64ui-pt-vec-and \
riscv_andi_vec_timer \ rv64ui-pt-vec-andi \
riscv_lui_vec_timer \ rv64ui-pt-vec-lui \
riscv_or_vec_timer \ rv64ui-pt-vec-or \
riscv_ori_vec_timer \ rv64ui-pt-vec-ori \
riscv_slt_vec_timer \ rv64ui-pt-vec-slt \
riscv_sltu_vec_timer \ rv64ui-pt-vec-sltu \
riscv_slti_vec_timer \ rv64ui-pt-vec-slti \
riscv_sltiu_vec_timer \ rv64ui-pt-vec-sltiu \
riscv_slli_vec_timer \ rv64ui-pt-vec-slli \
riscv_sll_vec_timer \ rv64ui-pt-vec-sll \
riscv_slliw_vec_timer \ rv64ui-pt-vec-slliw \
riscv_sllw_vec_timer \ rv64ui-pt-vec-sllw \
riscv_srai_vec_timer \ rv64ui-pt-vec-srai \
riscv_sra_vec_timer \ rv64ui-pt-vec-sra \
riscv_sraiw_vec_timer \ rv64ui-pt-vec-sraiw \
riscv_sraw_vec_timer \ rv64ui-pt-vec-sraw \
riscv_srli_vec_timer \ rv64ui-pt-vec-srli \
riscv_srl_vec_timer \ rv64ui-pt-vec-srl \
riscv_srliw_vec_timer \ rv64ui-pt-vec-srliw \
riscv_srlw_vec_timer \ rv64ui-pt-vec-srlw \
riscv_sub_vec_timer \ rv64ui-pt-vec-sub \
riscv_subw_vec_timer \ rv64ui-pt-vec-subw \
riscv_xor_vec_timer \ rv64ui-pt-vec-xor \
riscv_xori_vec_timer \ rv64ui-pt-vec-xori \
riscv_fadd_vec_timer \ rv64uf-pt-vec-fadd \
riscv_fsgnj_vec_timer \ rv64uf-pt-vec-fsgnj \
riscv_fmin_vec_timer \ rv64uf-pt-vec-fmin \
riscv_fmadd_vec_timer \ rv64uf-pt-vec-fmadd \
riscv_fcvt_w_vec_timer \ rv64uf-pt-vec-fcvt_w \
riscv_fcvt_vec_timer \ rv64uf-pt-vec-fcvt \
riscv_fcmp_vec_timer \ rv64uf-pt-vec-fcmp \
# Globally installed benchmarks # Globally installed benchmarks
global_bmarkdir = $(basedir)/riscv-asmtests-bmarks/riscv-bmarks bmarkdir = $(basedir)/riscv-asmtests-bmarks/riscv-bmarks
global_bmarks = \ bmarks = \
median.riscv \ median.riscv \
multiply.riscv \ multiply.riscv \
qsort.riscv \ qsort.riscv \
@ -506,8 +505,8 @@ global_bmarks = \
vec_cmplxmult.riscv \ vec_cmplxmult.riscv \
vec_matmul.riscv \ vec_matmul.riscv \
global_vec_bmarkdir = $(basedir)/../../riscv-app/misc/build vec_bmarkdir = $(basedir)/../../riscv-app/misc/build
global_vec_bmarks = \ vec_bmarks = \
ubmark-vvadd \ ubmark-vvadd \
ubmark-bin-search \ ubmark-bin-search \
ubmark-cmplx-mult \ ubmark-cmplx-mult \

22
emulator/Makefile
View File

@ -56,11 +56,11 @@ test:
%.riscv.hex: % %.riscv.hex: %
$(MAKE) -C $(dir $@) $(notdir $@) $(MAKE) -C $(dir $@) $(notdir $@)
$(addprefix output/, $(addsuffix .hex, $(global_asm_tests) $(global_asm_vm_tests) $(global_vecasm_tests) $(global_vecasm_vm_tests) $(global_vecasm_timer_tests))): output/%.hex: $(global_tstdir)/%.hex $(addprefix output/, $(addsuffix .hex, $(asm_p_tests) $(asm_v_tests) $(vecasm_p_tests) $(vecasm_v_tests) $(vecasm_pt_tests))): output/%.hex: $(tstdir)/%.hex
mkdir -p output mkdir -p output
ln -fs ../$< $@ ln -fs ../$< $@
$(addprefix output/, $(addsuffix .hex, $(global_bmarks))): output/%.hex: $(global_bmarkdir)/%.hex $(addprefix output/, $(addsuffix .hex, $(bmarks))): output/%.hex: $(bmarkdir)/%.hex
mkdir -p output mkdir -p output
ln -fs ../$< $@ ln -fs ../$< $@
@ -78,24 +78,24 @@ output/%.vpd: output/%.hex emulator-debug
vcd2vpd $@.vcd $@ > /dev/null & vcd2vpd $@.vcd $@ > /dev/null &
./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@) ./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@)
run-asm-tests: $(addprefix output/, $(addsuffix .out, $(global_asm_tests) $(global_asm_vm_tests))) run-asm-tests: $(addprefix output/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
run-vecasm-tests: $(addprefix output/, $(addsuffix .out, $(global_vecasm_tests) $(global_vecasm_vm_tests))) run-vecasm-tests: $(addprefix output/, $(addsuffix .out, $(vecasm_p_tests) $(vecasm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
run-vecasm-timer-tests: $(addprefix output/, $(addsuffix .out, $(global_vecasm_timer_tests))) run-vecasm-timer-tests: $(addprefix output/, $(addsuffix .out, $(vecasm_pt_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
run-bmarks-test: $(addprefix output/, $(addsuffix .out, $(global_bmarks))) run-bmarks-test: $(addprefix output/, $(addsuffix .out, $(bmarks)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
run-asm-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(global_asm_tests) $(global_asm_vm_tests))) run-asm-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(asm_p_tests) $(asm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run-vecasm-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(global_vecasm_tests) $(global_vecasm_vm_tests))) run-vecasm-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(vecasm_p_tests) $(vecasm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run-vecasm-timer-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(global_vecasm_timer_tests))) run-vecasm-timer-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(vecasm_pt_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run-bmarks-test-debug: $(addprefix output/, $(addsuffix .vpd, $(global_bmarks))) run-bmarks-test-debug: $(addprefix output/, $(addsuffix .vpd, $(bmarks)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run: run-asm-tests run-vecasm-tests run-vecasm-timer-tests run-bmarks-test run: run-asm-tests run-vecasm-tests run-vecasm-timer-tests run-bmarks-test
run-debug: run-asm-tests-debug run-vecasm-tests-debug run-vecasm-timer-tests-debug run-bmarks-test-debug run-debug: run-asm-tests-debug run-vecasm-tests-debug run-vecasm-timer-tests-debug run-bmarks-test-debug
run-fast: $(addprefix output/, $(addsuffix .run, $(global_asm_tests) $(global_asm_vm_tests) $(global_bmarks))) run-fast: $(addprefix output/, $(addsuffix .run, $(asm_p_tests) $(asm_v_tests) $(bmarks)))

1
riscv-tests Submodule

@ -0,0 +1 @@
Subproject commit f8ea498f79ab4d6495f2966d1e5c3dd42f567752