removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
This commit is contained in:
Henry Cook
parent
ebdc0a2692
commit
910b3b203a
@ -3,10 +3,9 @@ package rocket
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import Chisel._
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import Util._
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import Node._
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import uncore.constants.AddressConstants._
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case class BTBConfig(entries: Int, nras: Int = 0) {
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val matchBits = PGIDX_BITS
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case class BTBConfig(as: uncore.AddressSpaceConfiguration, entries: Int, nras: Int = 0) {
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val matchBits = as.pgIdxBits
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val pages0 = 1 max log2Up(entries) // is this sensible?
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val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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@ -56,9 +55,9 @@ class BHT(implicit conf: BTBConfig) {
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class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = VADDR_BITS)
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val target = UInt(width = VADDR_BITS)
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val returnAddr = UInt(width = VADDR_BITS)
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val pc = UInt(width = conf.as.vaddrBits)
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val target = UInt(width = conf.as.vaddrBits)
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val returnAddr = UInt(width = conf.as.vaddrBits)
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val taken = Bool()
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val isJump = Bool()
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val isCall = Bool()
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@ -70,7 +69,7 @@ class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
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class BTBResp(implicit conf: BTBConfig) extends Bundle {
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val taken = Bool()
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val target = UInt(width = VADDR_BITS)
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val target = UInt(width = conf.as.vaddrBits)
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val entry = UInt(width = conf.opaqueBits)
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val bht = new BHTResp
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@ -80,7 +79,7 @@ class BTBResp(implicit conf: BTBConfig) extends Bundle {
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// fully-associative branch target buffer
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class BTB(implicit conf: BTBConfig) extends Module {
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val io = new Bundle {
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val req = UInt(INPUT, VADDR_BITS)
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val req = UInt(INPUT, conf.as.vaddrBits)
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val invalidate = Bool(INPUT)
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@ -91,7 +90,7 @@ class BTB(implicit conf: BTBConfig) extends Module {
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val idxPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val tgts = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val tgtPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val pages = Vec.fill(conf.pages){Reg(UInt(width=VADDR_BITS-conf.matchBits))}
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val pages = Vec.fill(conf.pages){Reg(UInt(width=conf.as.vaddrBits-conf.matchBits))}
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val pageValid = Vec.fill(conf.pages){Reg(init=Bool(false))}
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val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
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@ -3,14 +3,13 @@ package rocket
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import Chisel._
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import Util._
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import uncore.HTIFIO
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import uncore.constants.MemoryOpConstants._
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class RocketIO(implicit conf: RocketConfiguration) extends Bundle
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{
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val host = new HTIFIO(conf.tl.ln.nClients)
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val imem = new CPUFrontendIO()(conf.icache)
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val dmem = new HellaCacheIO()(conf.dcache)
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val ptw = new DatapathPTWIO().flip
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val ptw = new DatapathPTWIO()(conf.as).flip
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val rocc = new RoCCInterface().flip
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}
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@ -4,7 +4,7 @@ import Chisel._
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import Util._
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import Node._
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import uncore.HTIFIO
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import uncore.constants.AddressConstants._
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import uncore.AddressSpaceConfiguration
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import scala.math._
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class Status extends Bundle {
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@ -45,14 +45,14 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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}
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val status = new Status().asOutput
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val ptbr = UInt(OUTPUT, PADDR_BITS)
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val evec = UInt(OUTPUT, VADDR_BITS+1)
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val ptbr = UInt(OUTPUT, conf.as.paddrBits)
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val evec = UInt(OUTPUT, conf.as.vaddrBits+1)
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val exception = Bool(INPUT)
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val retire = UInt(INPUT, log2Up(1+conf.retireWidth))
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val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth)))
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val cause = UInt(INPUT, conf.xprlen)
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val badvaddr_wen = Bool(INPUT)
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val pc = UInt(INPUT, VADDR_BITS+1)
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val pc = UInt(INPUT, conf.as.vaddrBits+1)
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val sret = Bool(INPUT)
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val fatc = Bool(OUTPUT)
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val replay = Bool(OUTPUT)
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@ -62,16 +62,16 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val rocc = new RoCCInterface().flip
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}
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val reg_epc = Reg(Bits(width = VADDR_BITS+1))
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val reg_badvaddr = Reg(Bits(width = VADDR_BITS))
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val reg_evec = Reg(Bits(width = VADDR_BITS))
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val reg_epc = Reg(Bits(width = conf.as.vaddrBits+1))
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val reg_badvaddr = Reg(Bits(width = conf.as.vaddrBits))
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val reg_evec = Reg(Bits(width = conf.as.vaddrBits))
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val reg_compare = Reg(Bits(width = 32))
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val reg_cause = Reg(Bits(width = conf.xprlen))
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val reg_tohost = Reg(init=Bits(0, conf.xprlen))
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val reg_fromhost = Reg(init=Bits(0, conf.xprlen))
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val reg_sup0 = Reg(Bits(width = conf.xprlen))
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val reg_sup1 = Reg(Bits(width = conf.xprlen))
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val reg_ptbr = Reg(UInt(width = PADDR_BITS))
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val reg_ptbr = Reg(UInt(width = conf.as.paddrBits))
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val reg_stats = Reg(init=Bool(false))
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val reg_status = Reg(new Status) // reset down below
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val reg_time = WideCounter(conf.xprlen)
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@ -130,7 +130,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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when (io.badvaddr_wen) {
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val wdata = io.rw.wdata
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val (upper, lower) = Split(wdata, VADDR_BITS)
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val (upper, lower) = Split(wdata, conf.as.vaddrBits)
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val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
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reg_badvaddr := Cat(sign, lower).toSInt
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}
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@ -161,7 +161,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) }
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val read_impl = Bits(2)
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val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
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val read_ptbr = reg_ptbr(conf.as.paddrBits-1, conf.as.pgIdxBits) << conf.as.pgIdxBits
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val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
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CSRs.fflags -> (if (!conf.fpu.isEmpty) reg_fflags else UInt(0)),
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@ -213,8 +213,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
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when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
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when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
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when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt }
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when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt }
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when (decoded_addr(CSRs.epc)) { reg_epc := wdata(conf.as.vaddrBits,0).toSInt }
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when (decoded_addr(CSRs.evec)) { reg_evec := wdata(conf.as.vaddrBits-1,0).toSInt }
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when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
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when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
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when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
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@ -222,7 +222,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
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when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata }
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when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata }
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when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt }
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when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(conf.as.paddrBits-1, conf.as.pgIdxBits), Bits(0, conf.as.pgIdxBits)).toUInt }
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when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
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}
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@ -4,10 +4,10 @@ import Chisel._
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import Instructions._
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import Util._
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import uncore.HTIFIO
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import uncore.constants.AddressConstants._
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class Datapath(implicit conf: RocketConfiguration) extends Module
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{
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implicit val as = conf.as
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val io = new Bundle {
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val host = new HTIFIO(conf.tl.ln.nClients)
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val ctrl = (new CtrlDpathIO).flip
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@ -158,10 +158,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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io.fpu.fromint_data := ex_rs(0)
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def vaSign(a0: UInt, ea: Bits) = {
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// efficient means to compress 64-bit VA into VADDR_BITS+1 bits
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// (VA is bad if VA(VADDR_BITS) != VA(VADDR_BITS-1))
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val a = a0 >> VADDR_BITS-1
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val e = ea(VADDR_BITS,VADDR_BITS-1)
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// efficient means to compress 64-bit VA into conf.as.vaddrBits+1 bits
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// (VA is bad if VA(conf.as.vaddrBits) != VA(conf.as.vaddrBits-1))
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val a = a0 >> conf.as.vaddrBits-1
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val e = ea(conf.as.vaddrBits,conf.as.vaddrBits-1)
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Mux(a === UInt(0) || a === UInt(1), e != UInt(0),
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Mux(a === SInt(-1) || a === SInt(-2), e === SInt(-1),
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e(0)))
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@ -169,7 +169,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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// D$ request interface (registered inside D$ module)
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// other signals (req_val, req_rdy) connect to control module
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io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
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io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(conf.as.vaddrBits-1,0)).toUInt
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io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
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require(io.dmem.req.bits.tag.getWidth >= 6)
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require(conf.dcacheReqTagBits >= 6)
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@ -240,7 +240,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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val mem_br_target = mem_reg_pc +
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Mux(io.ctrl.mem_branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst),
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Mux(!io.ctrl.mem_jalr && !io.ctrl.mem_branch, imm(IMM_UJ, mem_reg_inst), SInt(4)))
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val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(VADDR_BITS-1,0)), mem_br_target)
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val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(conf.as.vaddrBits-1,0)), mem_br_target)
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io.ctrl.mem_misprediction := mem_npc != Mux(io.ctrl.ex_valid, ex_reg_pc, id_pc)
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io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1
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val mem_int_wdata = Mux(io.ctrl.mem_jalr, mem_br_target, mem_reg_wdata)
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@ -5,33 +5,37 @@ import uncore._
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import Util._
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case class ICacheConfig(sets: Int, assoc: Int,
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ibytes: Int = 4,
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ntlb: Int = 8, btb: BTBConfig = BTBConfig(8),
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ibytes: Int = 4, rowbytes: Int = 64,
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ntlb: Int = 8,
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tl: TileLinkConfiguration,
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as: AddressSpaceConfiguration,
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btb: BTBConfig,
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code: Code = new IdentityCode)
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{
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val w = 1
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val dm = assoc == 1
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val lines = sets * assoc
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val databits = tl.dataBits
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val idxbits = log2Up(sets)
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val offbits = OFFSET_BITS
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val offbits = log2Up(tl.dataBits/8)
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val rowbits = rowbytes*8
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val rowoffbits = log2Up(rowbytes)
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val untagbits = idxbits + offbits
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val tagbits = PADDR_BITS - untagbits
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def refillcycles = CACHE_DATA_SIZE_IN_BYTES*8/tl.dataBits
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val tagbits = as.paddrBits - untagbits
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val refillcycles = tl.dataBits/rowbits
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require(isPow2(sets) && isPow2(assoc))
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require(isPow2(w) && isPow2(ibytes))
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require(PGIDX_BITS >= untagbits)
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require(as.pgIdxBits >= untagbits)
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}
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class FrontendReq extends Bundle {
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val pc = UInt(width = VADDR_BITS+1)
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class FrontendReq()(implicit conf: ICacheConfig) extends Bundle {
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val pc = UInt(width = conf.as.vaddrBits+1)
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override def clone = new FrontendReq().asInstanceOf[this.type]
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}
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class FrontendResp(implicit conf: ICacheConfig) extends Bundle {
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val pc = UInt(width = VADDR_BITS+1) // ID stage PC
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val pc = UInt(width = conf.as.vaddrBits+1) // ID stage PC
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val data = Bits(width = conf.ibytes*8)
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val xcpt_ma = Bool()
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val xcpt_if = Bool()
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@ -44,12 +48,13 @@ class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle {
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val resp = Decoupled(new FrontendResp).flip
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val btb_resp = Valid(new BTBResp()(conf.btb)).flip
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val btb_update = Valid(new BTBUpdate()(conf.btb))
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val ptw = new TLBPTWIO().flip
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val ptw = new TLBPTWIO()(conf.as).flip
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val invalidate = Bool(OUTPUT)
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}
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class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
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class Frontend(implicit c: ICacheConfig) extends Module
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{
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implicit val (tl, as) = (c.tl, c.as)
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val io = new Bundle {
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val cpu = new CPUFrontendIO()(c).flip
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val mem = new UncachedTileLinkIO
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@ -68,13 +73,14 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
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val s2_xcpt_if = Reg(init=Bool(false))
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val btbTarget = Cat(btb.io.resp.bits.target(VADDR_BITS-1), btb.io.resp.bits.target)
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val msb = c.as.vaddrBits-1
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val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
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val pcp4_0 = s1_pc + UInt(c.ibytes)
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val pcp4 = Cat(s1_pc(VADDR_BITS-1) & pcp4_0(VADDR_BITS-1), pcp4_0(VADDR_BITS-1,0))
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val pcp4 = Cat(s1_pc(msb) & pcp4_0(msb), pcp4_0(msb,0))
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val icmiss = s2_valid && !icache.io.resp.valid
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val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, pcp4)
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val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
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val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & (c.databits/8)) === (s1_pc & (c.databits/8)))
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val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & c.rowbytes) === (s1_pc & c.rowbytes))
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val stall = io.cpu.resp.valid && !io.cpu.resp.ready
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when (!stall) {
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@ -100,7 +106,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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tlb.io.ptw <> io.cpu.ptw
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tlb.io.req.valid := !stall && !icmiss
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tlb.io.req.bits.vpn := s1_pc >> UInt(PGIDX_BITS)
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tlb.io.req.bits.vpn := s1_pc >> UInt(c.as.pgIdxBits)
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tlb.io.req.bits.asid := UInt(0)
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.instruction := Bool(true)
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@ -115,7 +121,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
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io.cpu.resp.bits.pc := s2_pc & SInt(-c.ibytes) // discard PC LSBs
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io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8))
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io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(c.rowbytes)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8))
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io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(c.ibytes)-1,0) != UInt(0)
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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@ -123,15 +129,16 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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io.cpu.btb_resp.bits := s2_btb_resp_bits
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}
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class ICacheReq extends Bundle {
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val idx = UInt(width = PGIDX_BITS)
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val ppn = UInt(width = PPN_BITS) // delayed one cycle
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class ICacheReq(implicit c: ICacheConfig) extends Bundle {
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val idx = UInt(width = c.as.pgIdxBits)
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val ppn = UInt(width = c.as.ppnBits) // delayed one cycle
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val kill = Bool() // delayed one cycle
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override def clone = new ICacheReq().asInstanceOf[this.type]
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}
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class ICacheResp(implicit c: ICacheConfig) extends Bundle {
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val data = Bits(width = c.ibytes*8)
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val datablock = Bits(width = c.databits)
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val datablock = Bits(width = c.rowbits)
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override def clone = new ICacheResp().asInstanceOf[this.type]
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}
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@ -152,11 +159,11 @@ class ICache(implicit c: ICacheConfig) extends Module
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val rdy = Bool()
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val s2_valid = Reg(init=Bool(false))
|
||||
val s2_addr = Reg(UInt(width = PADDR_BITS))
|
||||
val s2_addr = Reg(UInt(width = c.as.paddrBits))
|
||||
val s2_any_tag_hit = Bool()
|
||||
|
||||
val s1_valid = Reg(init=Bool(false))
|
||||
val s1_pgoff = Reg(UInt(width = PGIDX_BITS))
|
||||
val s1_pgoff = Reg(UInt(width = c.as.pgIdxBits))
|
||||
val s1_addr = Cat(io.req.bits.ppn, s1_pgoff).toUInt
|
||||
val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits)
|
||||
|
||||
@ -231,7 +238,7 @@ class ICache(implicit c: ICacheConfig) extends Module
|
||||
s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
|
||||
|
||||
for (i <- 0 until c.assoc) {
|
||||
val data_array = Mem(Bits(width = c.code.width(c.databits)), c.sets*c.refillcycles, seqRead = true)
|
||||
val data_array = Mem(Bits(width = c.code.width(c.rowbits)), c.sets*c.refillcycles, seqRead = true)
|
||||
val s1_raddr = Reg(UInt())
|
||||
when (io.mem.grant.valid && repl_way === UInt(i)) {
|
||||
val d = io.mem.grant.bits.payload.data
|
||||
@ -245,7 +252,7 @@ class ICache(implicit c: ICacheConfig) extends Module
|
||||
// if s1_tag_match is critical, replace with partial tag check
|
||||
when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) }
|
||||
}
|
||||
val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0))
|
||||
val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.rowbytes)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0))
|
||||
io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
|
||||
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
|
||||
|
||||
|
||||
@ -7,41 +7,41 @@ import Util._
|
||||
case class DCacheConfig(sets: Int, ways: Int,
|
||||
nmshr: Int, nrpq: Int, nsdq: Int, ntlb: Int,
|
||||
tl: TileLinkConfiguration,
|
||||
as: AddressSpaceConfiguration,
|
||||
reqtagbits: Int, databits: Int,
|
||||
rowwords: Int = 8,
|
||||
code: Code = new IdentityCode,
|
||||
narrowRead: Boolean = true,
|
||||
reqtagbits: Int = -1, databits: Int = -1)
|
||||
narrowRead: Boolean = true)
|
||||
{
|
||||
require(states > 0)
|
||||
require(OFFSET_BITS == log2Up(CACHE_DATA_SIZE_IN_BYTES))
|
||||
require(OFFSET_BITS <= ACQUIRE_WRITE_MASK_BITS)
|
||||
require(log2Up(OFFSET_BITS) <= ACQUIRE_SUBWORD_ADDR_BITS)
|
||||
require(isPow2(sets))
|
||||
require(isPow2(ways)) // TODO: relax this
|
||||
def states = tl.co.nClientStates
|
||||
def lines = sets*ways
|
||||
def dm = ways == 1
|
||||
def ppnbits = PADDR_BITS - PGIDX_BITS
|
||||
def vpnbits = VADDR_BITS - PGIDX_BITS
|
||||
def pgidxbits = PGIDX_BITS
|
||||
def offbits = OFFSET_BITS
|
||||
def offbits = log2Up(tl.dataBits/8)
|
||||
def ppnbits = as.ppnBits
|
||||
def vpnbits = as.vpnBits
|
||||
def pgidxbits = as.pgIdxBits
|
||||
def maxaddrbits = ppnbits.max(vpnbits+1) + pgidxbits
|
||||
def paddrbits = ppnbits + pgidxbits
|
||||
def paddrbits = as.paddrBits
|
||||
def lineaddrbits = paddrbits - offbits
|
||||
def idxbits = log2Up(sets)
|
||||
def waybits = log2Up(ways)
|
||||
def untagbits = offbits + idxbits
|
||||
def tagbits = lineaddrbits - idxbits
|
||||
def ramoffbits = log2Up(tl.dataBits/8)
|
||||
def databytes = databits/8
|
||||
def wordoffbits = log2Up(databytes)
|
||||
def isNarrowRead = narrowRead && databits*ways % tl.dataBits == 0
|
||||
def refillcycles = CACHE_DATA_SIZE_IN_BYTES*8/tl.dataBits
|
||||
def rowbits = rowwords*databits
|
||||
def rowbytes = rowwords*databytes
|
||||
def rowoffbits = log2Up(rowbytes)
|
||||
def refillcycles = tl.dataBits/(rowwords*databits)
|
||||
def isNarrowRead = narrowRead && databits*ways % rowbits == 0
|
||||
val statebits = log2Up(states)
|
||||
val metabits = statebits + tagbits
|
||||
val encdatabits = code.width(databits)
|
||||
val encmetabits = code.width(metabits)
|
||||
val wordsperrow = tl.dataBits/databits
|
||||
val bitsperrow = wordsperrow*encdatabits
|
||||
val encrowbits = rowwords*encdatabits
|
||||
val lrsc_cycles = 32 // ISA requires 16-insn LRSC sequences to succeed
|
||||
}
|
||||
|
||||
@ -118,8 +118,8 @@ class DataReadReq(implicit val conf: DCacheConfig) extends DCacheBundle {
|
||||
class DataWriteReq(implicit val conf: DCacheConfig) extends DCacheBundle {
|
||||
val way_en = Bits(width = conf.ways)
|
||||
val addr = Bits(width = conf.untagbits)
|
||||
val wmask = Bits(width = conf.wordsperrow)
|
||||
val data = Bits(width = conf.bitsperrow)
|
||||
val wmask = Bits(width = conf.rowwords)
|
||||
val data = Bits(width = conf.encrowbits)
|
||||
}
|
||||
|
||||
class InternalProbe(implicit conf: DCacheConfig) extends Probe()(conf.tl) {
|
||||
@ -273,7 +273,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
|
||||
|
||||
io.idx_match := (state != s_invalid) && idx_match
|
||||
io.mem_resp := req
|
||||
io.mem_resp.addr := (if(conf.refillcycles > 1) Cat(req_idx, refill_count) else req_idx) << conf.ramoffbits
|
||||
io.mem_resp.addr := (if(conf.refillcycles > 1) Cat(req_idx, refill_count) else req_idx) << conf.rowoffbits
|
||||
io.tag := req.addr >> conf.untagbits
|
||||
io.req_pri_rdy := state === s_invalid
|
||||
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
|
||||
@ -426,7 +426,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
|
||||
val req = Decoupled(new WritebackReq()).flip
|
||||
val meta_read = Decoupled(new MetaReadReq)
|
||||
val data_req = Decoupled(new DataReadReq())
|
||||
val data_resp = Bits(INPUT, conf.bitsperrow)
|
||||
val data_resp = Bits(INPUT, conf.encrowbits)
|
||||
val release = Decoupled(new Release)
|
||||
}
|
||||
|
||||
@ -471,7 +471,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
|
||||
io.data_req.valid := fire
|
||||
io.data_req.bits.way_en := req.way_en
|
||||
io.data_req.bits.addr := (if(conf.refillcycles > 1) Cat(req.idx, cnt(log2Up(conf.refillcycles)-1,0))
|
||||
else req.idx) << conf.ramoffbits
|
||||
else req.idx) << conf.rowoffbits
|
||||
|
||||
io.release.valid := valid && r2_data_req_fired
|
||||
io.release.bits.r_type := req.r_type
|
||||
@ -599,39 +599,39 @@ class DataArray(implicit conf: DCacheConfig) extends Module {
|
||||
val io = new Bundle {
|
||||
val read = Decoupled(new DataReadReq).flip
|
||||
val write = Decoupled(new DataWriteReq).flip
|
||||
val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.bitsperrow)}
|
||||
val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.encrowbits)}
|
||||
}
|
||||
|
||||
val waddr = io.write.bits.addr >> conf.ramoffbits
|
||||
val raddr = io.read.bits.addr >> conf.ramoffbits
|
||||
val waddr = io.write.bits.addr >> conf.rowoffbits
|
||||
val raddr = io.read.bits.addr >> conf.rowoffbits
|
||||
|
||||
if (conf.isNarrowRead) {
|
||||
for (w <- 0 until conf.ways by conf.wordsperrow) {
|
||||
val wway_en = io.write.bits.way_en(w+conf.wordsperrow-1,w)
|
||||
val rway_en = io.read.bits.way_en(w+conf.wordsperrow-1,w)
|
||||
val resp = Vec.fill(conf.wordsperrow){Bits(width = conf.bitsperrow)}
|
||||
for (w <- 0 until conf.ways by conf.rowwords) {
|
||||
val wway_en = io.write.bits.way_en(w+conf.rowwords-1,w)
|
||||
val rway_en = io.read.bits.way_en(w+conf.rowwords-1,w)
|
||||
val resp = Vec.fill(conf.rowwords){Bits(width = conf.encrowbits)}
|
||||
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
|
||||
for (p <- 0 until resp.size) {
|
||||
val array = Mem(Bits(width=conf.bitsperrow), conf.sets*conf.refillcycles, seqRead = true)
|
||||
val array = Mem(Bits(width=conf.encrowbits), conf.sets*conf.refillcycles, seqRead = true)
|
||||
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
|
||||
val data = Fill(conf.wordsperrow, io.write.bits.data(conf.encdatabits*(p+1)-1,conf.encdatabits*p))
|
||||
val data = Fill(conf.rowwords, io.write.bits.data(conf.encdatabits*(p+1)-1,conf.encdatabits*p))
|
||||
val mask = FillInterleaved(conf.encdatabits, wway_en)
|
||||
array.write(waddr, data, mask)
|
||||
}
|
||||
resp(p) := array(RegEnable(raddr, rway_en.orR && io.read.valid))
|
||||
}
|
||||
for (dw <- 0 until conf.wordsperrow) {
|
||||
for (dw <- 0 until conf.rowwords) {
|
||||
val r = AVec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw)))
|
||||
val resp_mux =
|
||||
if (r.size == 1) r
|
||||
else AVec(r(r_raddr(conf.ramoffbits-1,conf.wordoffbits)), r.tail:_*)
|
||||
else AVec(r(r_raddr(conf.rowoffbits-1,conf.wordoffbits)), r.tail:_*)
|
||||
io.resp(w+dw) := resp_mux.toBits
|
||||
}
|
||||
}
|
||||
} else {
|
||||
val wmask = FillInterleaved(conf.encdatabits, io.write.bits.wmask)
|
||||
for (w <- 0 until conf.ways) {
|
||||
val array = Mem(Bits(width=conf.bitsperrow), conf.sets*conf.refillcycles, seqRead = true)
|
||||
val array = Mem(Bits(width=conf.encrowbits), conf.sets*conf.refillcycles, seqRead = true)
|
||||
when (io.write.bits.way_en(w) && io.write.valid) {
|
||||
array.write(waddr, io.write.bits.data, wmask)
|
||||
}
|
||||
@ -723,7 +723,7 @@ class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
|
||||
val resp = Valid(new HellaCacheResp).flip
|
||||
val replay_next = Valid(Bits(width = conf.reqtagbits)).flip
|
||||
val xcpt = (new HellaCacheExceptions).asInput
|
||||
val ptw = (new TLBPTWIO).flip
|
||||
val ptw = new TLBPTWIO()(conf.as).flip
|
||||
val ordered = Bool(INPUT)
|
||||
}
|
||||
|
||||
@ -766,7 +766,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
val s1_sc = s1_req.cmd === M_XSC
|
||||
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
|
||||
|
||||
val dtlb = Module(new TLB(8))
|
||||
val dtlb = Module(new TLB(8)(conf.as))
|
||||
dtlb.io.ptw <> io.cpu.ptw
|
||||
dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys
|
||||
dtlb.io.req.bits.passthrough := s1_req.phys
|
||||
@ -834,7 +834,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
data.io.write.valid := writeArb.io.out.valid
|
||||
writeArb.io.out.ready := data.io.write.ready
|
||||
data.io.write.bits := writeArb.io.out.bits
|
||||
val wdata_encoded = (0 until conf.wordsperrow).map(i => conf.code.encode(writeArb.io.out.bits.data(conf.databits*(i+1)-1,conf.databits*i)))
|
||||
val wdata_encoded = (0 until conf.rowwords).map(i => conf.code.encode(writeArb.io.out.bits.data(conf.databits*(i+1)-1,conf.databits*i)))
|
||||
data.io.write.bits.data := AVec(wdata_encoded).toBits
|
||||
|
||||
// tag read for new requests
|
||||
@ -885,9 +885,9 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
}
|
||||
when (io.cpu.ptw.sret) { lrsc_count := 0 }
|
||||
|
||||
val s2_data = Vec.fill(conf.ways){Bits(width = conf.bitsperrow)}
|
||||
val s2_data = Vec.fill(conf.ways){Bits(width = conf.encrowbits)}
|
||||
for (w <- 0 until conf.ways) {
|
||||
val regs = Vec.fill(conf.wordsperrow){Reg(Bits(width = conf.encdatabits))}
|
||||
val regs = Vec.fill(conf.rowwords){Reg(Bits(width = conf.encdatabits))}
|
||||
val en1 = s1_clk_en && s1_tag_eq_way(w)
|
||||
for (i <- 0 until regs.size) {
|
||||
val en = en1 && (Bool(i == 0 || !conf.isNarrowRead) || s1_writeback)
|
||||
@ -896,10 +896,10 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
s2_data(w) := regs.toBits
|
||||
}
|
||||
val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data)
|
||||
val s2_data_decoded = (0 until conf.wordsperrow).map(i => conf.code.decode(s2_data_muxed(conf.encdatabits*(i+1)-1,conf.encdatabits*i)))
|
||||
val s2_data_decoded = (0 until conf.rowwords).map(i => conf.code.decode(s2_data_muxed(conf.encdatabits*(i+1)-1,conf.encdatabits*i)))
|
||||
val s2_data_corrected = AVec(s2_data_decoded.map(_.corrected)).toBits
|
||||
val s2_data_uncorrected = AVec(s2_data_decoded.map(_.uncorrected)).toBits
|
||||
val s2_word_idx = if (conf.isNarrowRead) UInt(0) else s2_req.addr(log2Up(conf.wordsperrow*conf.databytes)-1,3)
|
||||
val s2_word_idx = if (conf.isNarrowRead) UInt(0) else s2_req.addr(log2Up(conf.rowwords*conf.databytes)-1,3)
|
||||
val s2_data_correctable = AVec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx)
|
||||
|
||||
// store/amo hits
|
||||
@ -912,8 +912,8 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
}
|
||||
|
||||
writeArb.io.in(0).bits.addr := s3_req.addr
|
||||
writeArb.io.in(0).bits.wmask := UInt(1) << s3_req.addr(conf.ramoffbits-1,offsetlsb).toUInt
|
||||
writeArb.io.in(0).bits.data := Fill(conf.wordsperrow, s3_req.data)
|
||||
writeArb.io.in(0).bits.wmask := UInt(1) << s3_req.addr(conf.rowoffbits-1,offsetlsb).toUInt
|
||||
writeArb.io.in(0).bits.data := Fill(conf.rowwords, s3_req.data)
|
||||
writeArb.io.in(0).valid := s3_valid
|
||||
writeArb.io.in(0).bits.way_en := s3_way
|
||||
|
||||
|
||||
@ -1,27 +1,27 @@
|
||||
package rocket
|
||||
|
||||
import Chisel._
|
||||
import uncore.constants.AddressConstants._
|
||||
import uncore.constants.MemoryOpConstants._
|
||||
import uncore._
|
||||
import Util._
|
||||
|
||||
class PTWResp extends Bundle {
|
||||
class PTWResp()(implicit conf: AddressSpaceConfiguration) extends Bundle {
|
||||
val error = Bool()
|
||||
val ppn = UInt(width = PPN_BITS)
|
||||
val perm = Bits(width = PERM_BITS)
|
||||
val ppn = UInt(width = conf.ppnBits)
|
||||
val perm = Bits(width = conf.permBits)
|
||||
|
||||
override def clone = new PTWResp().asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class TLBPTWIO extends Bundle {
|
||||
val req = Decoupled(UInt(width = VPN_BITS))
|
||||
class TLBPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
|
||||
val req = Decoupled(UInt(width = conf.vpnBits))
|
||||
val resp = Valid(new PTWResp).flip
|
||||
|
||||
val status = new Status().asInput
|
||||
val invalidate = Bool(INPUT)
|
||||
val sret = Bool(INPUT)
|
||||
}
|
||||
|
||||
class DatapathPTWIO extends Bundle {
|
||||
val ptbr = UInt(INPUT, PADDR_BITS)
|
||||
class DatapathPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
|
||||
val ptbr = UInt(INPUT, conf.paddrBits)
|
||||
val invalidate = Bool(INPUT)
|
||||
val sret = Bool(INPUT)
|
||||
val status = new Status().asInput
|
||||
@ -29,6 +29,7 @@ class DatapathPTWIO extends Bundle {
|
||||
|
||||
class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
|
||||
{
|
||||
implicit val as = conf.as
|
||||
val io = new Bundle {
|
||||
val requestor = Vec.fill(n){new TLBPTWIO}.flip
|
||||
val mem = new HellaCacheIO()(conf.dcache)
|
||||
@ -36,8 +37,8 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
|
||||
}
|
||||
|
||||
val levels = 3
|
||||
val bitsPerLevel = VPN_BITS/levels
|
||||
require(VPN_BITS == levels * bitsPerLevel)
|
||||
val bitsPerLevel = conf.as.vpnBits/levels
|
||||
require(conf.as.vpnBits == levels * bitsPerLevel)
|
||||
|
||||
val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5)
|
||||
val state = Reg(init=s_ready)
|
||||
@ -49,14 +50,14 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
|
||||
|
||||
val vpn_idx = AVec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count)
|
||||
|
||||
val arb = Module(new RRArbiter(UInt(width = VPN_BITS), n))
|
||||
val arb = Module(new RRArbiter(UInt(width = conf.as.vpnBits), n))
|
||||
arb.io.in <> io.requestor.map(_.req)
|
||||
arb.io.out.ready := state === s_ready
|
||||
|
||||
when (arb.io.out.fire()) {
|
||||
r_req_vpn := arb.io.out.bits
|
||||
r_req_dest := arb.io.chosen
|
||||
r_pte := Cat(io.dpath.ptbr(PADDR_BITS-1,PGIDX_BITS), io.mem.resp.bits.data(PGIDX_BITS-1,0))
|
||||
r_pte := Cat(io.dpath.ptbr(conf.as.paddrBits-1,conf.as.pgIdxBits), io.mem.resp.bits.data(conf.as.pgIdxBits-1,0))
|
||||
}
|
||||
|
||||
when (io.mem.resp.valid) {
|
||||
@ -67,13 +68,13 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
|
||||
io.mem.req.bits.phys := Bool(true)
|
||||
io.mem.req.bits.cmd := M_XRD
|
||||
io.mem.req.bits.typ := MT_D
|
||||
io.mem.req.bits.addr := Cat(r_pte(PADDR_BITS-1,PGIDX_BITS), vpn_idx).toUInt << log2Up(conf.xprlen/8)
|
||||
io.mem.req.bits.addr := Cat(r_pte(conf.as.paddrBits-1,conf.as.pgIdxBits), vpn_idx).toUInt << log2Up(conf.xprlen/8)
|
||||
io.mem.req.bits.kill := Bool(false)
|
||||
|
||||
val resp_val = state === s_done || state === s_error
|
||||
val resp_err = state === s_error || state === s_wait
|
||||
|
||||
val r_resp_ppn = io.mem.req.bits.addr >> PGIDX_BITS
|
||||
val r_resp_ppn = io.mem.req.bits.addr >> conf.as.pgIdxBits
|
||||
val resp_ppn = AVec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count)
|
||||
|
||||
for (i <- 0 until io.requestor.size) {
|
||||
|
||||
@ -35,6 +35,7 @@ class RoCCResponse(implicit conf: RocketConfiguration) extends Bundle
|
||||
|
||||
class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
|
||||
{
|
||||
implicit val as = conf.as
|
||||
val cmd = Decoupled(new RoCCCommand).flip
|
||||
val resp = Decoupled(new RoCCResponse)
|
||||
val mem = new HellaCacheIO()(conf.dcache)
|
||||
|
||||
@ -4,7 +4,7 @@ import Chisel._
|
||||
import uncore._
|
||||
import Util._
|
||||
|
||||
case class RocketConfiguration(tl: TileLinkConfiguration,
|
||||
case class RocketConfiguration(tl: TileLinkConfiguration, as: AddressSpaceConfiguration,
|
||||
icache: ICacheConfig, dcache: DCacheConfig,
|
||||
fpu: Option[FPUConfig] = None,
|
||||
rocc: Option[RocketConfiguration => RoCC] = None,
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
package rocket
|
||||
|
||||
import Chisel._
|
||||
import uncore.constants.AddressConstants._
|
||||
import uncore.AddressSpaceConfiguration
|
||||
import scala.math._
|
||||
|
||||
class CAMIO(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
|
||||
@ -64,28 +64,30 @@ class PseudoLRU(n: Int)
|
||||
}
|
||||
}
|
||||
|
||||
class TLBReq extends Bundle
|
||||
class TLBReq()(implicit conf: AddressSpaceConfiguration) extends Bundle
|
||||
{
|
||||
val asid = UInt(width = ASID_BITS)
|
||||
val vpn = UInt(width = VPN_BITS+1)
|
||||
val asid = UInt(width = conf.asidBits)
|
||||
val vpn = UInt(width = conf.vpnBits+1)
|
||||
val passthrough = Bool()
|
||||
val instruction = Bool()
|
||||
|
||||
override def clone = new TLBReq().asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class TLBResp(entries: Int) extends Bundle
|
||||
class TLBResp(entries: Int)(implicit conf: AddressSpaceConfiguration) extends Bundle
|
||||
{
|
||||
// lookup responses
|
||||
val miss = Bool(OUTPUT)
|
||||
val hit_idx = UInt(OUTPUT, entries)
|
||||
val ppn = UInt(OUTPUT, PPN_BITS)
|
||||
val ppn = UInt(OUTPUT, conf.ppnBits)
|
||||
val xcpt_ld = Bool(OUTPUT)
|
||||
val xcpt_st = Bool(OUTPUT)
|
||||
val xcpt_if = Bool(OUTPUT)
|
||||
|
||||
override def clone = new TLBResp(entries).asInstanceOf[this.type]
|
||||
override def clone = new TLBResp(entries)(conf).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class TLB(entries: Int) extends Module
|
||||
class TLB(entries: Int)(implicit conf: AddressSpaceConfiguration) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val req = Decoupled(new TLBReq).flip
|
||||
@ -98,7 +100,7 @@ class TLB(entries: Int) extends Module
|
||||
val r_refill_tag = Reg(UInt())
|
||||
val r_refill_waddr = Reg(UInt())
|
||||
|
||||
val tag_cam = Module(new RocketCAM(entries, ASID_BITS+VPN_BITS))
|
||||
val tag_cam = Module(new RocketCAM(entries, conf.asidBits+conf.vpnBits))
|
||||
val tag_ram = Vec.fill(entries){Reg(io.ptw.resp.bits.ppn.clone)}
|
||||
|
||||
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
|
||||
@ -135,7 +137,7 @@ class TLB(entries: Int) extends Module
|
||||
val plru = new PseudoLRU(entries)
|
||||
val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace)
|
||||
|
||||
val bad_va = io.req.bits.vpn(VPN_BITS) != io.req.bits.vpn(VPN_BITS-1)
|
||||
val bad_va = io.req.bits.vpn(conf.vpnBits) != io.req.bits.vpn(conf.vpnBits-1)
|
||||
val tlb_hit = io.ptw.status.vm && tag_hit
|
||||
val tlb_miss = io.ptw.status.vm && !tag_hit && !bad_va
|
||||
|
||||
@ -148,7 +150,7 @@ class TLB(entries: Int) extends Module
|
||||
io.resp.xcpt_st := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sw_array & tag_cam.io.hits).orR, (uw_array & tag_cam.io.hits).orR)
|
||||
io.resp.xcpt_if := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sx_array & tag_cam.io.hits).orR, (ux_array & tag_cam.io.hits).orR)
|
||||
io.resp.miss := tlb_miss
|
||||
io.resp.ppn := Mux(io.ptw.status.vm && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(PPN_BITS-1,0))
|
||||
io.resp.ppn := Mux(io.ptw.status.vm && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(conf.ppnBits-1,0))
|
||||
io.resp.hit_idx := tag_cam.io.hits
|
||||
|
||||
io.ptw.req.valid := state === s_request
|
||||
|
||||
Loading…
Reference in New Issue
Block a user