riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants

Browse Source
This commit is contained in:
Henry Cook
2014-04-01 17:15:46 -07:00
parent ebdc0a2692
commit 910b3b203a
10 changed files with 135 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
rocket/src/main/scala/btb.scala
View File

@@ -3,10 +3,9 @@ package rocket
import Chisel._ import Chisel._
import Util._ import Util._
import Node._ import Node._
import uncore.constants.AddressConstants._
case class BTBConfig(entries: Int, nras: Int = 0) { case class BTBConfig(as: uncore.AddressSpaceConfiguration, entries: Int, nras: Int = 0) {
val matchBits = PGIDX_BITS val matchBits = as.pgIdxBits
val pages0 = 1 max log2Up(entries) // is this sensible? val pages0 = 1 max log2Up(entries) // is this sensible?
val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages
val opaqueBits = log2Up(entries) val opaqueBits = log2Up(entries)
@@ -56,9 +55,9 @@ class BHT(implicit conf: BTBConfig) {
class BTBUpdate(implicit conf: BTBConfig) extends Bundle { class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
val prediction = Valid(new BTBResp) val prediction = Valid(new BTBResp)
val pc = UInt(width = VADDR_BITS) val pc = UInt(width = conf.as.vaddrBits)
val target = UInt(width = VADDR_BITS) val target = UInt(width = conf.as.vaddrBits)
val returnAddr = UInt(width = VADDR_BITS) val returnAddr = UInt(width = conf.as.vaddrBits)
val taken = Bool() val taken = Bool()
val isJump = Bool() val isJump = Bool()
val isCall = Bool() val isCall = Bool()
@@ -70,7 +69,7 @@ class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
class BTBResp(implicit conf: BTBConfig) extends Bundle { class BTBResp(implicit conf: BTBConfig) extends Bundle {
val taken = Bool() val taken = Bool()
val target = UInt(width = VADDR_BITS) val target = UInt(width = conf.as.vaddrBits)
val entry = UInt(width = conf.opaqueBits) val entry = UInt(width = conf.opaqueBits)
val bht = new BHTResp val bht = new BHTResp
@@ -80,7 +79,7 @@ class BTBResp(implicit conf: BTBConfig) extends Bundle {
// fully-associative branch target buffer // fully-associative branch target buffer
class BTB(implicit conf: BTBConfig) extends Module { class BTB(implicit conf: BTBConfig) extends Module {
val io = new Bundle { val io = new Bundle {
val req = UInt(INPUT, VADDR_BITS) val req = UInt(INPUT, conf.as.vaddrBits)
val resp = Valid(new BTBResp) val resp = Valid(new BTBResp)
val update = Valid(new BTBUpdate).flip val update = Valid(new BTBUpdate).flip
val invalidate = Bool(INPUT) val invalidate = Bool(INPUT)
@@ -91,7 +90,7 @@ class BTB(implicit conf: BTBConfig) extends Module {
val idxPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))} val idxPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
val tgts = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))} val tgts = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
val tgtPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))} val tgtPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
val pages = Vec.fill(conf.pages){Reg(UInt(width=VADDR_BITS-conf.matchBits))} val pages = Vec.fill(conf.pages){Reg(UInt(width=conf.as.vaddrBits-conf.matchBits))}
val pageValid = Vec.fill(conf.pages){Reg(init=Bool(false))} val pageValid = Vec.fill(conf.pages){Reg(init=Bool(false))}
val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0)) val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0)) val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))

3
rocket/src/main/scala/core.scala
View File

@@ -3,14 +3,13 @@ package rocket
import Chisel._ import Chisel._
import Util._ import Util._
import uncore.HTIFIO import uncore.HTIFIO
import uncore.constants.MemoryOpConstants._
class RocketIO(implicit conf: RocketConfiguration) extends Bundle class RocketIO(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new HTIFIO(conf.tl.ln.nClients) val host = new HTIFIO(conf.tl.ln.nClients)
val imem = new CPUFrontendIO()(conf.icache) val imem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache) val dmem = new HellaCacheIO()(conf.dcache)
val ptw = new DatapathPTWIO().flip val ptw = new DatapathPTWIO()(conf.as).flip
val rocc = new RoCCInterface().flip val rocc = new RoCCInterface().flip
} }

26
rocket/src/main/scala/csr.scala
View File

@@ -4,7 +4,7 @@ import Chisel._
import Util._ import Util._
import Node._ import Node._
import uncore.HTIFIO import uncore.HTIFIO
import uncore.constants.AddressConstants._ import uncore.AddressSpaceConfiguration
import scala.math._ import scala.math._
class Status extends Bundle { class Status extends Bundle {
@@ -45,14 +45,14 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
} }
val status = new Status().asOutput val status = new Status().asOutput
val ptbr = UInt(OUTPUT, PADDR_BITS) val ptbr = UInt(OUTPUT, conf.as.paddrBits)
val evec = UInt(OUTPUT, VADDR_BITS+1) val evec = UInt(OUTPUT, conf.as.vaddrBits+1)
val exception = Bool(INPUT) val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+conf.retireWidth)) val retire = UInt(INPUT, log2Up(1+conf.retireWidth))
val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth))) val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth)))
val cause = UInt(INPUT, conf.xprlen) val cause = UInt(INPUT, conf.xprlen)
val badvaddr_wen = Bool(INPUT) val badvaddr_wen = Bool(INPUT)
val pc = UInt(INPUT, VADDR_BITS+1) val pc = UInt(INPUT, conf.as.vaddrBits+1)
val sret = Bool(INPUT) val sret = Bool(INPUT)
val fatc = Bool(OUTPUT) val fatc = Bool(OUTPUT)
val replay = Bool(OUTPUT) val replay = Bool(OUTPUT)
@@ -62,16 +62,16 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val rocc = new RoCCInterface().flip val rocc = new RoCCInterface().flip
} }
val reg_epc = Reg(Bits(width = VADDR_BITS+1)) val reg_epc = Reg(Bits(width = conf.as.vaddrBits+1))
val reg_badvaddr = Reg(Bits(width = VADDR_BITS)) val reg_badvaddr = Reg(Bits(width = conf.as.vaddrBits))
val reg_evec = Reg(Bits(width = VADDR_BITS)) val reg_evec = Reg(Bits(width = conf.as.vaddrBits))
val reg_compare = Reg(Bits(width = 32)) val reg_compare = Reg(Bits(width = 32))
val reg_cause = Reg(Bits(width = conf.xprlen)) val reg_cause = Reg(Bits(width = conf.xprlen))
val reg_tohost = Reg(init=Bits(0, conf.xprlen)) val reg_tohost = Reg(init=Bits(0, conf.xprlen))
val reg_fromhost = Reg(init=Bits(0, conf.xprlen)) val reg_fromhost = Reg(init=Bits(0, conf.xprlen))
val reg_sup0 = Reg(Bits(width = conf.xprlen)) val reg_sup0 = Reg(Bits(width = conf.xprlen))
val reg_sup1 = Reg(Bits(width = conf.xprlen)) val reg_sup1 = Reg(Bits(width = conf.xprlen))
val reg_ptbr = Reg(UInt(width = PADDR_BITS)) val reg_ptbr = Reg(UInt(width = conf.as.paddrBits))
val reg_stats = Reg(init=Bool(false)) val reg_stats = Reg(init=Bool(false))
val reg_status = Reg(new Status) // reset down below val reg_status = Reg(new Status) // reset down below
val reg_time = WideCounter(conf.xprlen) val reg_time = WideCounter(conf.xprlen)
@@ -130,7 +130,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
when (io.badvaddr_wen) { when (io.badvaddr_wen) {
val wdata = io.rw.wdata val wdata = io.rw.wdata
val (upper, lower) = Split(wdata, VADDR_BITS) val (upper, lower) = Split(wdata, conf.as.vaddrBits)
val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR) val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
reg_badvaddr := Cat(sign, lower).toSInt reg_badvaddr := Cat(sign, lower).toSInt
} }
@@ -161,7 +161,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) } when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) }
val read_impl = Bits(2) val read_impl = Bits(2)
val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS val read_ptbr = reg_ptbr(conf.as.paddrBits-1, conf.as.pgIdxBits) << conf.as.pgIdxBits
val read_mapping = collection.mutable.LinkedHashMap[Int,Bits]( val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
CSRs.fflags -> (if (!conf.fpu.isEmpty) reg_fflags else UInt(0)), CSRs.fflags -> (if (!conf.fpu.isEmpty) reg_fflags else UInt(0)),
@@ -213,8 +213,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata } when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { reg_frm := wdata } when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth } when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt } when (decoded_addr(CSRs.epc)) { reg_epc := wdata(conf.as.vaddrBits,0).toSInt }
when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt } when (decoded_addr(CSRs.evec)) { reg_evec := wdata(conf.as.vaddrBits-1,0).toSInt }
when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt } when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) } when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } } when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
@@ -222,7 +222,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) } when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata } when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata } when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata }
when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt } when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(conf.as.paddrBits-1, conf.as.pgIdxBits), Bits(0, conf.as.pgIdxBits)).toUInt }
when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) } when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
} }

14
rocket/src/main/scala/dpath.scala
View File

@@ -4,10 +4,10 @@ import Chisel._
import Instructions._ import Instructions._
import Util._ import Util._
import uncore.HTIFIO import uncore.HTIFIO
import uncore.constants.AddressConstants._
class Datapath(implicit conf: RocketConfiguration) extends Module class Datapath(implicit conf: RocketConfiguration) extends Module
{ {
implicit val as = conf.as
val io = new Bundle { val io = new Bundle {
val host = new HTIFIO(conf.tl.ln.nClients) val host = new HTIFIO(conf.tl.ln.nClients)
val ctrl = (new CtrlDpathIO).flip val ctrl = (new CtrlDpathIO).flip
@@ -158,10 +158,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.fpu.fromint_data := ex_rs(0) io.fpu.fromint_data := ex_rs(0)
def vaSign(a0: UInt, ea: Bits) = { def vaSign(a0: UInt, ea: Bits) = {
// efficient means to compress 64-bit VA into VADDR_BITS+1 bits // efficient means to compress 64-bit VA into conf.as.vaddrBits+1 bits
// (VA is bad if VA(VADDR_BITS) != VA(VADDR_BITS-1)) // (VA is bad if VA(conf.as.vaddrBits) != VA(conf.as.vaddrBits-1))
val a = a0 >> VADDR_BITS-1 val a = a0 >> conf.as.vaddrBits-1
val e = ea(VADDR_BITS,VADDR_BITS-1) val e = ea(conf.as.vaddrBits,conf.as.vaddrBits-1)
Mux(a === UInt(0) || a === UInt(1), e != UInt(0), Mux(a === UInt(0) || a === UInt(1), e != UInt(0),
Mux(a === SInt(-1) || a === SInt(-2), e === SInt(-1), Mux(a === SInt(-1) || a === SInt(-2), e === SInt(-1),
e(0))) e(0)))
@@ -169,7 +169,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
// D$ request interface (registered inside D$ module) // D$ request interface (registered inside D$ module)
// other signals (req_val, req_rdy) connect to control module // other signals (req_val, req_rdy) connect to control module
io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(conf.as.vaddrBits-1,0)).toUInt
io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val) io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
require(io.dmem.req.bits.tag.getWidth >= 6) require(io.dmem.req.bits.tag.getWidth >= 6)
require(conf.dcacheReqTagBits >= 6) require(conf.dcacheReqTagBits >= 6)
@@ -240,7 +240,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val mem_br_target = mem_reg_pc + val mem_br_target = mem_reg_pc +
Mux(io.ctrl.mem_branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst), Mux(io.ctrl.mem_branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst),
Mux(!io.ctrl.mem_jalr && !io.ctrl.mem_branch, imm(IMM_UJ, mem_reg_inst), SInt(4))) Mux(!io.ctrl.mem_jalr && !io.ctrl.mem_branch, imm(IMM_UJ, mem_reg_inst), SInt(4)))
val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(VADDR_BITS-1,0)), mem_br_target) val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(conf.as.vaddrBits-1,0)), mem_br_target)
io.ctrl.mem_misprediction := mem_npc != Mux(io.ctrl.ex_valid, ex_reg_pc, id_pc) io.ctrl.mem_misprediction := mem_npc != Mux(io.ctrl.ex_valid, ex_reg_pc, id_pc)
io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1 io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1
val mem_int_wdata = Mux(io.ctrl.mem_jalr, mem_br_target, mem_reg_wdata) val mem_int_wdata = Mux(io.ctrl.mem_jalr, mem_br_target, mem_reg_wdata)

57
rocket/src/main/scala/icache.scala
View File

@@ -5,33 +5,37 @@ import uncore._
import Util._ import Util._
case class ICacheConfig(sets: Int, assoc: Int, case class ICacheConfig(sets: Int, assoc: Int,
ibytes: Int = 4, ibytes: Int = 4, rowbytes: Int = 64,
ntlb: Int = 8, btb: BTBConfig = BTBConfig(8), ntlb: Int = 8,
tl: TileLinkConfiguration, tl: TileLinkConfiguration,
as: AddressSpaceConfiguration,
btb: BTBConfig,
code: Code = new IdentityCode) code: Code = new IdentityCode)
{ {
val w = 1 val w = 1
val dm = assoc == 1 val dm = assoc == 1
val lines = sets * assoc val lines = sets * assoc
val databits = tl.dataBits
val idxbits = log2Up(sets) val idxbits = log2Up(sets)
val offbits = OFFSET_BITS val offbits = log2Up(tl.dataBits/8)
val rowbits = rowbytes*8
val rowoffbits = log2Up(rowbytes)
val untagbits = idxbits + offbits val untagbits = idxbits + offbits
val tagbits = PADDR_BITS - untagbits val tagbits = as.paddrBits - untagbits
def refillcycles = CACHE_DATA_SIZE_IN_BYTES*8/tl.dataBits val refillcycles = tl.dataBits/rowbits
require(isPow2(sets) && isPow2(assoc)) require(isPow2(sets) && isPow2(assoc))
require(isPow2(w) && isPow2(ibytes)) require(isPow2(w) && isPow2(ibytes))
require(PGIDX_BITS >= untagbits) require(as.pgIdxBits >= untagbits)
} }
class FrontendReq extends Bundle { class FrontendReq()(implicit conf: ICacheConfig) extends Bundle {
val pc = UInt(width = VADDR_BITS+1) val pc = UInt(width = conf.as.vaddrBits+1)
override def clone = new FrontendReq().asInstanceOf[this.type]
} }
class FrontendResp(implicit conf: ICacheConfig) extends Bundle { class FrontendResp(implicit conf: ICacheConfig) extends Bundle {
val pc = UInt(width = VADDR_BITS+1) // ID stage PC val pc = UInt(width = conf.as.vaddrBits+1) // ID stage PC
val data = Bits(width = conf.ibytes*8) val data = Bits(width = conf.ibytes*8)
val xcpt_ma = Bool() val xcpt_ma = Bool()
val xcpt_if = Bool() val xcpt_if = Bool()
@@ -44,12 +48,13 @@ class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle {
val resp = Decoupled(new FrontendResp).flip val resp = Decoupled(new FrontendResp).flip
val btb_resp = Valid(new BTBResp()(conf.btb)).flip val btb_resp = Valid(new BTBResp()(conf.btb)).flip
val btb_update = Valid(new BTBUpdate()(conf.btb)) val btb_update = Valid(new BTBUpdate()(conf.btb))
val ptw = new TLBPTWIO().flip val ptw = new TLBPTWIO()(conf.as).flip
val invalidate = Bool(OUTPUT) val invalidate = Bool(OUTPUT)
} }
class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module class Frontend(implicit c: ICacheConfig) extends Module
{ {
implicit val (tl, as) = (c.tl, c.as)
val io = new Bundle { val io = new Bundle {
val cpu = new CPUFrontendIO()(c).flip val cpu = new CPUFrontendIO()(c).flip
val mem = new UncachedTileLinkIO val mem = new UncachedTileLinkIO
@@ -68,13 +73,14 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone) val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
val s2_xcpt_if = Reg(init=Bool(false)) val s2_xcpt_if = Reg(init=Bool(false))
val btbTarget = Cat(btb.io.resp.bits.target(VADDR_BITS-1), btb.io.resp.bits.target) val msb = c.as.vaddrBits-1
val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
val pcp4_0 = s1_pc + UInt(c.ibytes) val pcp4_0 = s1_pc + UInt(c.ibytes)
val pcp4 = Cat(s1_pc(VADDR_BITS-1) & pcp4_0(VADDR_BITS-1), pcp4_0(VADDR_BITS-1,0)) val pcp4 = Cat(s1_pc(msb) & pcp4_0(msb), pcp4_0(msb,0))
val icmiss = s2_valid && !icache.io.resp.valid val icmiss = s2_valid && !icache.io.resp.valid
val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, pcp4) val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, pcp4)
val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & (c.databits/8)) === (s1_pc & (c.databits/8))) val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & c.rowbytes) === (s1_pc & c.rowbytes))
val stall = io.cpu.resp.valid && !io.cpu.resp.ready val stall = io.cpu.resp.valid && !io.cpu.resp.ready
when (!stall) { when (!stall) {
@@ -100,7 +106,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
tlb.io.ptw <> io.cpu.ptw tlb.io.ptw <> io.cpu.ptw
tlb.io.req.valid := !stall && !icmiss tlb.io.req.valid := !stall && !icmiss
tlb.io.req.bits.vpn := s1_pc >> UInt(PGIDX_BITS) tlb.io.req.bits.vpn := s1_pc >> UInt(c.as.pgIdxBits)
tlb.io.req.bits.asid := UInt(0) tlb.io.req.bits.asid := UInt(0)
tlb.io.req.bits.passthrough := Bool(false) tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.instruction := Bool(true) tlb.io.req.bits.instruction := Bool(true)
@@ -115,7 +121,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid) io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
io.cpu.resp.bits.pc := s2_pc & SInt(-c.ibytes) // discard PC LSBs io.cpu.resp.bits.pc := s2_pc & SInt(-c.ibytes) // discard PC LSBs
io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)) io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(c.rowbytes)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8))
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(c.ibytes)-1,0) != UInt(0) io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(c.ibytes)-1,0) != UInt(0)
io.cpu.resp.bits.xcpt_if := s2_xcpt_if io.cpu.resp.bits.xcpt_if := s2_xcpt_if
@@ -123,15 +129,16 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
io.cpu.btb_resp.bits := s2_btb_resp_bits io.cpu.btb_resp.bits := s2_btb_resp_bits
} }
class ICacheReq extends Bundle { class ICacheReq(implicit c: ICacheConfig) extends Bundle {
val idx = UInt(width = PGIDX_BITS) val idx = UInt(width = c.as.pgIdxBits)
val ppn = UInt(width = PPN_BITS) // delayed one cycle val ppn = UInt(width = c.as.ppnBits) // delayed one cycle
val kill = Bool() // delayed one cycle val kill = Bool() // delayed one cycle
override def clone = new ICacheReq().asInstanceOf[this.type]
} }
class ICacheResp(implicit c: ICacheConfig) extends Bundle { class ICacheResp(implicit c: ICacheConfig) extends Bundle {
val data = Bits(width = c.ibytes*8) val data = Bits(width = c.ibytes*8)
val datablock = Bits(width = c.databits) val datablock = Bits(width = c.rowbits)
override def clone = new ICacheResp().asInstanceOf[this.type] override def clone = new ICacheResp().asInstanceOf[this.type]
} }
@@ -152,11 +159,11 @@ class ICache(implicit c: ICacheConfig) extends Module
val rdy = Bool() val rdy = Bool()
val s2_valid = Reg(init=Bool(false)) val s2_valid = Reg(init=Bool(false))
val s2_addr = Reg(UInt(width = PADDR_BITS)) val s2_addr = Reg(UInt(width = c.as.paddrBits))
val s2_any_tag_hit = Bool() val s2_any_tag_hit = Bool()
val s1_valid = Reg(init=Bool(false)) val s1_valid = Reg(init=Bool(false))
val s1_pgoff = Reg(UInt(width = PGIDX_BITS)) val s1_pgoff = Reg(UInt(width = c.as.pgIdxBits))
val s1_addr = Cat(io.req.bits.ppn, s1_pgoff).toUInt val s1_addr = Cat(io.req.bits.ppn, s1_pgoff).toUInt
val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits) val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits)
@@ -231,7 +238,7 @@ class ICache(implicit c: ICacheConfig) extends Module
s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_) s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
for (i <- 0 until c.assoc) { for (i <- 0 until c.assoc) {
val data_array = Mem(Bits(width = c.code.width(c.databits)), c.sets*c.refillcycles, seqRead = true) val data_array = Mem(Bits(width = c.code.width(c.rowbits)), c.sets*c.refillcycles, seqRead = true)
val s1_raddr = Reg(UInt()) val s1_raddr = Reg(UInt())
when (io.mem.grant.valid && repl_way === UInt(i)) { when (io.mem.grant.valid && repl_way === UInt(i)) {
val d = io.mem.grant.bits.payload.data val d = io.mem.grant.bits.payload.data
@@ -245,7 +252,7 @@ class ICache(implicit c: ICacheConfig) extends Module
// if s1_tag_match is critical, replace with partial tag check // if s1_tag_match is critical, replace with partial tag check
when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) } when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) }
} }
val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0)) val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.rowbytes)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0))
io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word) io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout) io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)

82
rocket/src/main/scala/nbdcache.scala
View File

@@ -7,41 +7,41 @@ import Util._
case class DCacheConfig(sets: Int, ways: Int, case class DCacheConfig(sets: Int, ways: Int,
nmshr: Int, nrpq: Int, nsdq: Int, ntlb: Int, nmshr: Int, nrpq: Int, nsdq: Int, ntlb: Int,
tl: TileLinkConfiguration, tl: TileLinkConfiguration,
as: AddressSpaceConfiguration,
reqtagbits: Int, databits: Int,
rowwords: Int = 8,
code: Code = new IdentityCode, code: Code = new IdentityCode,
narrowRead: Boolean = true, narrowRead: Boolean = true)
reqtagbits: Int = -1, databits: Int = -1)
{ {
require(states > 0) require(states > 0)
require(OFFSET_BITS == log2Up(CACHE_DATA_SIZE_IN_BYTES))
require(OFFSET_BITS <= ACQUIRE_WRITE_MASK_BITS)
require(log2Up(OFFSET_BITS) <= ACQUIRE_SUBWORD_ADDR_BITS)
require(isPow2(sets)) require(isPow2(sets))
require(isPow2(ways)) // TODO: relax this require(isPow2(ways)) // TODO: relax this
def states = tl.co.nClientStates def states = tl.co.nClientStates
def lines = sets*ways def lines = sets*ways
def dm = ways == 1 def dm = ways == 1
def ppnbits = PADDR_BITS - PGIDX_BITS def offbits = log2Up(tl.dataBits/8)
def vpnbits = VADDR_BITS - PGIDX_BITS def ppnbits = as.ppnBits
def pgidxbits = PGIDX_BITS def vpnbits = as.vpnBits
def offbits = OFFSET_BITS def pgidxbits = as.pgIdxBits
def maxaddrbits = ppnbits.max(vpnbits+1) + pgidxbits def maxaddrbits = ppnbits.max(vpnbits+1) + pgidxbits
def paddrbits = ppnbits + pgidxbits def paddrbits = as.paddrBits
def lineaddrbits = paddrbits - offbits def lineaddrbits = paddrbits - offbits
def idxbits = log2Up(sets) def idxbits = log2Up(sets)
def waybits = log2Up(ways) def waybits = log2Up(ways)
def untagbits = offbits + idxbits def untagbits = offbits + idxbits
def tagbits = lineaddrbits - idxbits def tagbits = lineaddrbits - idxbits
def ramoffbits = log2Up(tl.dataBits/8)
def databytes = databits/8 def databytes = databits/8
def wordoffbits = log2Up(databytes) def wordoffbits = log2Up(databytes)
def isNarrowRead = narrowRead && databits*ways % tl.dataBits == 0 def rowbits = rowwords*databits
def refillcycles = CACHE_DATA_SIZE_IN_BYTES*8/tl.dataBits def rowbytes = rowwords*databytes
def rowoffbits = log2Up(rowbytes)
def refillcycles = tl.dataBits/(rowwords*databits)
def isNarrowRead = narrowRead && databits*ways % rowbits == 0
val statebits = log2Up(states) val statebits = log2Up(states)
val metabits = statebits + tagbits val metabits = statebits + tagbits
val encdatabits = code.width(databits) val encdatabits = code.width(databits)
val encmetabits = code.width(metabits) val encmetabits = code.width(metabits)
val wordsperrow = tl.dataBits/databits val encrowbits = rowwords*encdatabits
val bitsperrow = wordsperrow*encdatabits
val lrsc_cycles = 32 // ISA requires 16-insn LRSC sequences to succeed val lrsc_cycles = 32 // ISA requires 16-insn LRSC sequences to succeed
} }
@@ -118,8 +118,8 @@ class DataReadReq(implicit val conf: DCacheConfig) extends DCacheBundle {
class DataWriteReq(implicit val conf: DCacheConfig) extends DCacheBundle { class DataWriteReq(implicit val conf: DCacheConfig) extends DCacheBundle {
val way_en = Bits(width = conf.ways) val way_en = Bits(width = conf.ways)
val addr = Bits(width = conf.untagbits) val addr = Bits(width = conf.untagbits)
val wmask = Bits(width = conf.wordsperrow) val wmask = Bits(width = conf.rowwords)
val data = Bits(width = conf.bitsperrow) val data = Bits(width = conf.encrowbits)
} }
class InternalProbe(implicit conf: DCacheConfig) extends Probe()(conf.tl) { class InternalProbe(implicit conf: DCacheConfig) extends Probe()(conf.tl) {
@@ -273,7 +273,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
io.idx_match := (state != s_invalid) && idx_match io.idx_match := (state != s_invalid) && idx_match
io.mem_resp := req io.mem_resp := req
io.mem_resp.addr := (if(conf.refillcycles > 1) Cat(req_idx, refill_count) else req_idx) << conf.ramoffbits io.mem_resp.addr := (if(conf.refillcycles > 1) Cat(req_idx, refill_count) else req_idx) << conf.rowoffbits
io.tag := req.addr >> conf.untagbits io.tag := req.addr >> conf.untagbits
io.req_pri_rdy := state === s_invalid io.req_pri_rdy := state === s_invalid
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
@@ -426,7 +426,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
val req = Decoupled(new WritebackReq()).flip val req = Decoupled(new WritebackReq()).flip
val meta_read = Decoupled(new MetaReadReq) val meta_read = Decoupled(new MetaReadReq)
val data_req = Decoupled(new DataReadReq()) val data_req = Decoupled(new DataReadReq())
val data_resp = Bits(INPUT, conf.bitsperrow) val data_resp = Bits(INPUT, conf.encrowbits)
val release = Decoupled(new Release) val release = Decoupled(new Release)
} }
@@ -471,7 +471,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
io.data_req.valid := fire io.data_req.valid := fire
io.data_req.bits.way_en := req.way_en io.data_req.bits.way_en := req.way_en
io.data_req.bits.addr := (if(conf.refillcycles > 1) Cat(req.idx, cnt(log2Up(conf.refillcycles)-1,0)) io.data_req.bits.addr := (if(conf.refillcycles > 1) Cat(req.idx, cnt(log2Up(conf.refillcycles)-1,0))
else req.idx) << conf.ramoffbits else req.idx) << conf.rowoffbits
io.release.valid := valid && r2_data_req_fired io.release.valid := valid && r2_data_req_fired
io.release.bits.r_type := req.r_type io.release.bits.r_type := req.r_type
@@ -599,39 +599,39 @@ class DataArray(implicit conf: DCacheConfig) extends Module {
val io = new Bundle { val io = new Bundle {
val read = Decoupled(new DataReadReq).flip val read = Decoupled(new DataReadReq).flip
val write = Decoupled(new DataWriteReq).flip val write = Decoupled(new DataWriteReq).flip
val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.bitsperrow)} val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.encrowbits)}
} }
val waddr = io.write.bits.addr >> conf.ramoffbits val waddr = io.write.bits.addr >> conf.rowoffbits
val raddr = io.read.bits.addr >> conf.ramoffbits val raddr = io.read.bits.addr >> conf.rowoffbits
if (conf.isNarrowRead) { if (conf.isNarrowRead) {
for (w <- 0 until conf.ways by conf.wordsperrow) { for (w <- 0 until conf.ways by conf.rowwords) {
val wway_en = io.write.bits.way_en(w+conf.wordsperrow-1,w) val wway_en = io.write.bits.way_en(w+conf.rowwords-1,w)
val rway_en = io.read.bits.way_en(w+conf.wordsperrow-1,w) val rway_en = io.read.bits.way_en(w+conf.rowwords-1,w)
val resp = Vec.fill(conf.wordsperrow){Bits(width = conf.bitsperrow)} val resp = Vec.fill(conf.rowwords){Bits(width = conf.encrowbits)}
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid) val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
for (p <- 0 until resp.size) { for (p <- 0 until resp.size) {
val array = Mem(Bits(width=conf.bitsperrow), conf.sets*conf.refillcycles, seqRead = true) val array = Mem(Bits(width=conf.encrowbits), conf.sets*conf.refillcycles, seqRead = true)
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) { when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
val data = Fill(conf.wordsperrow, io.write.bits.data(conf.encdatabits*(p+1)-1,conf.encdatabits*p)) val data = Fill(conf.rowwords, io.write.bits.data(conf.encdatabits*(p+1)-1,conf.encdatabits*p))
val mask = FillInterleaved(conf.encdatabits, wway_en) val mask = FillInterleaved(conf.encdatabits, wway_en)
array.write(waddr, data, mask) array.write(waddr, data, mask)
} }
resp(p) := array(RegEnable(raddr, rway_en.orR && io.read.valid)) resp(p) := array(RegEnable(raddr, rway_en.orR && io.read.valid))
} }
for (dw <- 0 until conf.wordsperrow) { for (dw <- 0 until conf.rowwords) {
val r = AVec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw))) val r = AVec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw)))
val resp_mux = val resp_mux =
if (r.size == 1) r if (r.size == 1) r
else AVec(r(r_raddr(conf.ramoffbits-1,conf.wordoffbits)), r.tail:_*) else AVec(r(r_raddr(conf.rowoffbits-1,conf.wordoffbits)), r.tail:_*)
io.resp(w+dw) := resp_mux.toBits io.resp(w+dw) := resp_mux.toBits
} }
} }
} else { } else {
val wmask = FillInterleaved(conf.encdatabits, io.write.bits.wmask) val wmask = FillInterleaved(conf.encdatabits, io.write.bits.wmask)
for (w <- 0 until conf.ways) { for (w <- 0 until conf.ways) {
val array = Mem(Bits(width=conf.bitsperrow), conf.sets*conf.refillcycles, seqRead = true) val array = Mem(Bits(width=conf.encrowbits), conf.sets*conf.refillcycles, seqRead = true)
when (io.write.bits.way_en(w) && io.write.valid) { when (io.write.bits.way_en(w) && io.write.valid) {
array.write(waddr, io.write.bits.data, wmask) array.write(waddr, io.write.bits.data, wmask)
} }
@@ -723,7 +723,7 @@ class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
val resp = Valid(new HellaCacheResp).flip val resp = Valid(new HellaCacheResp).flip
val replay_next = Valid(Bits(width = conf.reqtagbits)).flip val replay_next = Valid(Bits(width = conf.reqtagbits)).flip
val xcpt = (new HellaCacheExceptions).asInput val xcpt = (new HellaCacheExceptions).asInput
val ptw = (new TLBPTWIO).flip val ptw = new TLBPTWIO()(conf.as).flip
val ordered = Bool(INPUT) val ordered = Bool(INPUT)
} }
@@ -766,7 +766,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
val s1_sc = s1_req.cmd === M_XSC val s1_sc = s1_req.cmd === M_XSC
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd) val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
val dtlb = Module(new TLB(8)) val dtlb = Module(new TLB(8)(conf.as))
dtlb.io.ptw <> io.cpu.ptw dtlb.io.ptw <> io.cpu.ptw
dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys
dtlb.io.req.bits.passthrough := s1_req.phys dtlb.io.req.bits.passthrough := s1_req.phys
@@ -834,7 +834,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
data.io.write.valid := writeArb.io.out.valid data.io.write.valid := writeArb.io.out.valid
writeArb.io.out.ready := data.io.write.ready writeArb.io.out.ready := data.io.write.ready
data.io.write.bits := writeArb.io.out.bits data.io.write.bits := writeArb.io.out.bits
val wdata_encoded = (0 until conf.wordsperrow).map(i => conf.code.encode(writeArb.io.out.bits.data(conf.databits*(i+1)-1,conf.databits*i))) val wdata_encoded = (0 until conf.rowwords).map(i => conf.code.encode(writeArb.io.out.bits.data(conf.databits*(i+1)-1,conf.databits*i)))
data.io.write.bits.data := AVec(wdata_encoded).toBits data.io.write.bits.data := AVec(wdata_encoded).toBits
// tag read for new requests // tag read for new requests
@@ -885,9 +885,9 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
} }
when (io.cpu.ptw.sret) { lrsc_count := 0 } when (io.cpu.ptw.sret) { lrsc_count := 0 }
val s2_data = Vec.fill(conf.ways){Bits(width = conf.bitsperrow)} val s2_data = Vec.fill(conf.ways){Bits(width = conf.encrowbits)}
for (w <- 0 until conf.ways) { for (w <- 0 until conf.ways) {
val regs = Vec.fill(conf.wordsperrow){Reg(Bits(width = conf.encdatabits))} val regs = Vec.fill(conf.rowwords){Reg(Bits(width = conf.encdatabits))}
val en1 = s1_clk_en && s1_tag_eq_way(w) val en1 = s1_clk_en && s1_tag_eq_way(w)
for (i <- 0 until regs.size) { for (i <- 0 until regs.size) {
val en = en1 && (Bool(i == 0 || !conf.isNarrowRead) || s1_writeback) val en = en1 && (Bool(i == 0 || !conf.isNarrowRead) || s1_writeback)
@@ -896,10 +896,10 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
s2_data(w) := regs.toBits s2_data(w) := regs.toBits
} }
val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data) val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data)
val s2_data_decoded = (0 until conf.wordsperrow).map(i => conf.code.decode(s2_data_muxed(conf.encdatabits*(i+1)-1,conf.encdatabits*i))) val s2_data_decoded = (0 until conf.rowwords).map(i => conf.code.decode(s2_data_muxed(conf.encdatabits*(i+1)-1,conf.encdatabits*i)))
val s2_data_corrected = AVec(s2_data_decoded.map(_.corrected)).toBits val s2_data_corrected = AVec(s2_data_decoded.map(_.corrected)).toBits
val s2_data_uncorrected = AVec(s2_data_decoded.map(_.uncorrected)).toBits val s2_data_uncorrected = AVec(s2_data_decoded.map(_.uncorrected)).toBits
val s2_word_idx = if (conf.isNarrowRead) UInt(0) else s2_req.addr(log2Up(conf.wordsperrow*conf.databytes)-1,3) val s2_word_idx = if (conf.isNarrowRead) UInt(0) else s2_req.addr(log2Up(conf.rowwords*conf.databytes)-1,3)
val s2_data_correctable = AVec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx) val s2_data_correctable = AVec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx)
// store/amo hits // store/amo hits
@@ -912,8 +912,8 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
} }
writeArb.io.in(0).bits.addr := s3_req.addr writeArb.io.in(0).bits.addr := s3_req.addr
writeArb.io.in(0).bits.wmask := UInt(1) << s3_req.addr(conf.ramoffbits-1,offsetlsb).toUInt writeArb.io.in(0).bits.wmask := UInt(1) << s3_req.addr(conf.rowoffbits-1,offsetlsb).toUInt
writeArb.io.in(0).bits.data := Fill(conf.wordsperrow, s3_req.data) writeArb.io.in(0).bits.data := Fill(conf.rowwords, s3_req.data)
writeArb.io.in(0).valid := s3_valid writeArb.io.in(0).valid := s3_valid
writeArb.io.in(0).bits.way_en := s3_way writeArb.io.in(0).bits.way_en := s3_way

33
rocket/src/main/scala/ptw.scala
View File

@@ -1,27 +1,27 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore.constants.AddressConstants._ import uncore._
import uncore.constants.MemoryOpConstants._
import Util._ import Util._
class PTWResp extends Bundle { class PTWResp()(implicit conf: AddressSpaceConfiguration) extends Bundle {
val error = Bool() val error = Bool()
val ppn = UInt(width = PPN_BITS) val ppn = UInt(width = conf.ppnBits)
val perm = Bits(width = PERM_BITS) val perm = Bits(width = conf.permBits)
override def clone = new PTWResp().asInstanceOf[this.type]
} }
class TLBPTWIO extends Bundle { class TLBPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
val req = Decoupled(UInt(width = VPN_BITS)) val req = Decoupled(UInt(width = conf.vpnBits))
val resp = Valid(new PTWResp).flip val resp = Valid(new PTWResp).flip
val status = new Status().asInput val status = new Status().asInput
val invalidate = Bool(INPUT) val invalidate = Bool(INPUT)
val sret = Bool(INPUT) val sret = Bool(INPUT)
} }
class DatapathPTWIO extends Bundle { class DatapathPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
val ptbr = UInt(INPUT, PADDR_BITS) val ptbr = UInt(INPUT, conf.paddrBits)
val invalidate = Bool(INPUT) val invalidate = Bool(INPUT)
val sret = Bool(INPUT) val sret = Bool(INPUT)
val status = new Status().asInput val status = new Status().asInput
@@ -29,6 +29,7 @@ class DatapathPTWIO extends Bundle {
class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
{ {
implicit val as = conf.as
val io = new Bundle { val io = new Bundle {
val requestor = Vec.fill(n){new TLBPTWIO}.flip val requestor = Vec.fill(n){new TLBPTWIO}.flip
val mem = new HellaCacheIO()(conf.dcache) val mem = new HellaCacheIO()(conf.dcache)
@@ -36,8 +37,8 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
} }
val levels = 3 val levels = 3
val bitsPerLevel = VPN_BITS/levels val bitsPerLevel = conf.as.vpnBits/levels
require(VPN_BITS == levels * bitsPerLevel) require(conf.as.vpnBits == levels * bitsPerLevel)
val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5) val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5)
val state = Reg(init=s_ready) val state = Reg(init=s_ready)
@@ -49,14 +50,14 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
val vpn_idx = AVec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count) val vpn_idx = AVec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count)
val arb = Module(new RRArbiter(UInt(width = VPN_BITS), n)) val arb = Module(new RRArbiter(UInt(width = conf.as.vpnBits), n))
arb.io.in <> io.requestor.map(_.req) arb.io.in <> io.requestor.map(_.req)
arb.io.out.ready := state === s_ready arb.io.out.ready := state === s_ready
when (arb.io.out.fire()) { when (arb.io.out.fire()) {
r_req_vpn := arb.io.out.bits r_req_vpn := arb.io.out.bits
r_req_dest := arb.io.chosen r_req_dest := arb.io.chosen
r_pte := Cat(io.dpath.ptbr(PADDR_BITS-1,PGIDX_BITS), io.mem.resp.bits.data(PGIDX_BITS-1,0)) r_pte := Cat(io.dpath.ptbr(conf.as.paddrBits-1,conf.as.pgIdxBits), io.mem.resp.bits.data(conf.as.pgIdxBits-1,0))
} }
when (io.mem.resp.valid) { when (io.mem.resp.valid) {
@@ -67,13 +68,13 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
io.mem.req.bits.phys := Bool(true) io.mem.req.bits.phys := Bool(true)
io.mem.req.bits.cmd := M_XRD io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.typ := MT_D io.mem.req.bits.typ := MT_D
io.mem.req.bits.addr := Cat(r_pte(PADDR_BITS-1,PGIDX_BITS), vpn_idx).toUInt << log2Up(conf.xprlen/8) io.mem.req.bits.addr := Cat(r_pte(conf.as.paddrBits-1,conf.as.pgIdxBits), vpn_idx).toUInt << log2Up(conf.xprlen/8)
io.mem.req.bits.kill := Bool(false) io.mem.req.bits.kill := Bool(false)
val resp_val = state === s_done || state === s_error val resp_val = state === s_done || state === s_error
val resp_err = state === s_error || state === s_wait val resp_err = state === s_error || state === s_wait
val r_resp_ppn = io.mem.req.bits.addr >> PGIDX_BITS val r_resp_ppn = io.mem.req.bits.addr >> conf.as.pgIdxBits
val resp_ppn = AVec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count) val resp_ppn = AVec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count)
for (i <- 0 until io.requestor.size) { for (i <- 0 until io.requestor.size) {

1
rocket/src/main/scala/rocc.scala
View File

@@ -35,6 +35,7 @@ class RoCCResponse(implicit conf: RocketConfiguration) extends Bundle
class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
{ {
implicit val as = conf.as
val cmd = Decoupled(new RoCCCommand).flip val cmd = Decoupled(new RoCCCommand).flip
val resp = Decoupled(new RoCCResponse) val resp = Decoupled(new RoCCResponse)
val mem = new HellaCacheIO()(conf.dcache) val mem = new HellaCacheIO()(conf.dcache)

2
rocket/src/main/scala/tile.scala
View File

@@ -4,7 +4,7 @@ import Chisel._
import uncore._ import uncore._
import Util._ import Util._
case class RocketConfiguration(tl: TileLinkConfiguration, case class RocketConfiguration(tl: TileLinkConfiguration, as: AddressSpaceConfiguration,
icache: ICacheConfig, dcache: DCacheConfig, icache: ICacheConfig, dcache: DCacheConfig,
fpu: Option[FPUConfig] = None, fpu: Option[FPUConfig] = None,
rocc: Option[RocketConfiguration => RoCC] = None, rocc: Option[RocketConfiguration => RoCC] = None,

24
rocket/src/main/scala/tlb.scala
View File

@@ -1,7 +1,7 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore.constants.AddressConstants._ import uncore.AddressSpaceConfiguration
import scala.math._ import scala.math._
class CAMIO(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle { class CAMIO(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
@@ -64,28 +64,30 @@ class PseudoLRU(n: Int)
} }
} }
class TLBReq extends Bundle class TLBReq()(implicit conf: AddressSpaceConfiguration) extends Bundle
{ {
val asid = UInt(width = ASID_BITS) val asid = UInt(width = conf.asidBits)
val vpn = UInt(width = VPN_BITS+1) val vpn = UInt(width = conf.vpnBits+1)
val passthrough = Bool() val passthrough = Bool()
val instruction = Bool() val instruction = Bool()
override def clone = new TLBReq().asInstanceOf[this.type]
} }
class TLBResp(entries: Int) extends Bundle class TLBResp(entries: Int)(implicit conf: AddressSpaceConfiguration) extends Bundle
{ {
// lookup responses // lookup responses
val miss = Bool(OUTPUT) val miss = Bool(OUTPUT)
val hit_idx = UInt(OUTPUT, entries) val hit_idx = UInt(OUTPUT, entries)
val ppn = UInt(OUTPUT, PPN_BITS) val ppn = UInt(OUTPUT, conf.ppnBits)
val xcpt_ld = Bool(OUTPUT) val xcpt_ld = Bool(OUTPUT)
val xcpt_st = Bool(OUTPUT) val xcpt_st = Bool(OUTPUT)
val xcpt_if = Bool(OUTPUT) val xcpt_if = Bool(OUTPUT)
override def clone = new TLBResp(entries).asInstanceOf[this.type] override def clone = new TLBResp(entries)(conf).asInstanceOf[this.type]
} }
class TLB(entries: Int) extends Module class TLB(entries: Int)(implicit conf: AddressSpaceConfiguration) extends Module
{ {
val io = new Bundle { val io = new Bundle {
val req = Decoupled(new TLBReq).flip val req = Decoupled(new TLBReq).flip
@@ -98,7 +100,7 @@ class TLB(entries: Int) extends Module
val r_refill_tag = Reg(UInt()) val r_refill_tag = Reg(UInt())
val r_refill_waddr = Reg(UInt()) val r_refill_waddr = Reg(UInt())
val tag_cam = Module(new RocketCAM(entries, ASID_BITS+VPN_BITS)) val tag_cam = Module(new RocketCAM(entries, conf.asidBits+conf.vpnBits))
val tag_ram = Vec.fill(entries){Reg(io.ptw.resp.bits.ppn.clone)} val tag_ram = Vec.fill(entries){Reg(io.ptw.resp.bits.ppn.clone)}
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
@@ -135,7 +137,7 @@ class TLB(entries: Int) extends Module
val plru = new PseudoLRU(entries) val plru = new PseudoLRU(entries)
val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace) val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace)
val bad_va = io.req.bits.vpn(VPN_BITS) != io.req.bits.vpn(VPN_BITS-1) val bad_va = io.req.bits.vpn(conf.vpnBits) != io.req.bits.vpn(conf.vpnBits-1)
val tlb_hit = io.ptw.status.vm && tag_hit val tlb_hit = io.ptw.status.vm && tag_hit
val tlb_miss = io.ptw.status.vm && !tag_hit && !bad_va val tlb_miss = io.ptw.status.vm && !tag_hit && !bad_va
@@ -148,7 +150,7 @@ class TLB(entries: Int) extends Module
io.resp.xcpt_st := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sw_array & tag_cam.io.hits).orR, (uw_array & tag_cam.io.hits).orR) io.resp.xcpt_st := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sw_array & tag_cam.io.hits).orR, (uw_array & tag_cam.io.hits).orR)
io.resp.xcpt_if := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sx_array & tag_cam.io.hits).orR, (ux_array & tag_cam.io.hits).orR) io.resp.xcpt_if := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sx_array & tag_cam.io.hits).orR, (ux_array & tag_cam.io.hits).orR)
io.resp.miss := tlb_miss io.resp.miss := tlb_miss
io.resp.ppn := Mux(io.ptw.status.vm && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(PPN_BITS-1,0)) io.resp.ppn := Mux(io.ptw.status.vm && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(conf.ppnBits-1,0))
io.resp.hit_idx := tag_cam.io.hits io.resp.hit_idx := tag_cam.io.hits
io.ptw.req.valid := state === s_request io.ptw.req.valid := state === s_request