riscv/rocket-chip
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removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants

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This commit is contained in:
Henry Cook
2014-04-01 17:15:46 -07:00
parent ebdc0a2692
commit 910b3b203a
10 changed files with 135 additions and 126 deletions
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35
rocket/src/main/scala/ptw.scala
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@ -1,27 +1,27 @@
package rocket
import Chisel._
import uncore.constants.AddressConstants._
import uncore.constants.MemoryOpConstants._
import uncore._
import Util._
class PTWResp extends Bundle {
val error = Bool()
val ppn = UInt(width = PPN_BITS)
val perm = Bits(width = PERM_BITS)
class PTWResp()(implicit conf: AddressSpaceConfiguration) extends Bundle {
val error = Bool()
val ppn = UInt(width = conf.ppnBits)
val perm = Bits(width = conf.permBits)
override def clone = new PTWResp().asInstanceOf[this.type]
}
class TLBPTWIO extends Bundle {
val req = Decoupled(UInt(width = VPN_BITS))
class TLBPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
val req = Decoupled(UInt(width = conf.vpnBits))
val resp = Valid(new PTWResp).flip
val status = new Status().asInput
val invalidate = Bool(INPUT)
val sret = Bool(INPUT)
}
class DatapathPTWIO extends Bundle {
val ptbr = UInt(INPUT, PADDR_BITS)
class DatapathPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
val ptbr = UInt(INPUT, conf.paddrBits)
val invalidate = Bool(INPUT)
val sret = Bool(INPUT)
val status = new Status().asInput
@ -29,6 +29,7 @@ class DatapathPTWIO extends Bundle {
class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
{
implicit val as = conf.as
val io = new Bundle {
val requestor = Vec.fill(n){new TLBPTWIO}.flip
val mem = new HellaCacheIO()(conf.dcache)
@ -36,8 +37,8 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
}
val levels = 3
val bitsPerLevel = VPN_BITS/levels
require(VPN_BITS == levels * bitsPerLevel)
val bitsPerLevel = conf.as.vpnBits/levels
require(conf.as.vpnBits == levels * bitsPerLevel)
val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5)
val state = Reg(init=s_ready)
@ -49,14 +50,14 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
val vpn_idx = AVec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count)
val arb = Module(new RRArbiter(UInt(width = VPN_BITS), n))
val arb = Module(new RRArbiter(UInt(width = conf.as.vpnBits), n))
arb.io.in <> io.requestor.map(_.req)
arb.io.out.ready := state === s_ready
when (arb.io.out.fire()) {
r_req_vpn := arb.io.out.bits
r_req_dest := arb.io.chosen
r_pte := Cat(io.dpath.ptbr(PADDR_BITS-1,PGIDX_BITS), io.mem.resp.bits.data(PGIDX_BITS-1,0))
r_pte := Cat(io.dpath.ptbr(conf.as.paddrBits-1,conf.as.pgIdxBits), io.mem.resp.bits.data(conf.as.pgIdxBits-1,0))
}
when (io.mem.resp.valid) {
@ -67,13 +68,13 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
io.mem.req.bits.phys := Bool(true)
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.typ := MT_D
io.mem.req.bits.addr := Cat(r_pte(PADDR_BITS-1,PGIDX_BITS), vpn_idx).toUInt << log2Up(conf.xprlen/8)
io.mem.req.bits.addr := Cat(r_pte(conf.as.paddrBits-1,conf.as.pgIdxBits), vpn_idx).toUInt << log2Up(conf.xprlen/8)
io.mem.req.bits.kill := Bool(false)
val resp_val = state === s_done || state === s_error
val resp_err = state === s_error || state === s_wait
val r_resp_ppn = io.mem.req.bits.addr >> PGIDX_BITS
val r_resp_ppn = io.mem.req.bits.addr >> conf.as.pgIdxBits
val resp_ppn = AVec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count)
for (i <- 0 until io.requestor.size) {