riscv/rocket-chip
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fix D$ read/write concurrency bug

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This commit is contained in:
Andrew Waterman
2012-11-27 02:42:27 -08:00
parent 9c857b83f0
commit 90cae54ac4
2 changed files with 13 additions and 16 deletions
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9
rocket/src/main/scala/nbdcache.scala
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@ -600,17 +600,18 @@ class DataArray(implicit conf: DCacheConfig) extends Component {
if (conf.isNarrowRead) {
val waysPerMem = MEM_DATA_BITS/conf.databits
for (w <- 0 until conf.ways by waysPerMem) {
val wway_en = io.write.bits.way_en(w+waysPerMem-1,w)
val rway_en = io.read.bits.way_en(w+waysPerMem-1,w)
val resp = Vec(MEM_DATA_BITS/conf.databits){Reg{Bits(width = MEM_DATA_BITS)}}
val r_raddr = RegEn(io.read.bits.addr, io.read.valid)
for (p <- 0 until resp.size) {
val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=MEM_DATA_BITS) }
val way_en = io.write.bits.way_en(w+waysPerMem-1,w)
when (way_en.orR && io.write.valid && io.write.bits.wmask(p)) {
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
val data = Fill(waysPerMem, io.write.bits.data(conf.databits*(p+1)-1,conf.databits*p))
val mask = FillInterleaved(conf.databits, way_en)
val mask = FillInterleaved(conf.databits, wway_en)
array.write(waddr, data, mask)
}
when (way_en.orR && io.read.valid) {
when (rway_en.orR && io.read.valid) {
resp(p) := array(raddr)
}
}