Gracefully handle empty ports in AddressDecoder
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@ -19,25 +19,27 @@ object AddressDecoder
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// Find the minimum subset of bits needed to disambiguate port addresses.
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// ie: inspecting only the bits in the output, you can look at an address
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// and decide to which port (outer Seq) the address belongs.
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def apply(ports: Ports, givenBits: BigInt = BigInt(0)): BigInt = if (ports.size <= 1) givenBits else {
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// Every port must have at least one address!
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ports.foreach { p => require (!p.isEmpty) }
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def apply(ports: Ports, givenBits: BigInt = BigInt(0)): BigInt = {
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val nonEmptyPorts = ports.filter(_.nonEmpty)
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if (nonEmptyPorts.size <= 1) {
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givenBits
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} else {
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// Verify the user did not give us an impossible problem
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ports.combinations(2).foreach { case Seq(x, y) =>
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nonEmptyPorts.combinations(2).foreach { case Seq(x, y) =>
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x.foreach { a => y.foreach { b =>
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require (!a.overlaps(b)) // it must be possible to disambiguate ports!
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} }
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}
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val maxBits = log2Ceil(ports.map(_.map(_.base).max).max)
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val maxBits = log2Ceil(nonEmptyPorts.map(_.map(_.base).max).max)
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val (bitsToTry, bitsToTake) = (0 to maxBits).map(BigInt(1) << _).partition(b => (givenBits & b) == 0)
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val partitions = Seq(ports.map(_.sorted).sorted(portOrder))
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val partitions = Seq(nonEmptyPorts.map(_.sorted).sorted(portOrder))
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val givenPartitions = bitsToTake.foldLeft(partitions) { (p, b) => partitionPartitions(p, b) }
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val selected = recurse(givenPartitions, bitsToTry.toSeq)
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val output = selected.reduceLeft(_ | _) | givenBits
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// Modify the AddressSets to allow the new wider match functions
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val widePorts = ports.map { _.map { _.widen(~output) } }
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val widePorts = nonEmptyPorts.map { _.map { _.widen(~output) } }
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// Verify that it remains possible to disambiguate all ports
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widePorts.combinations(2).foreach { case Seq(x, y) =>
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x.foreach { a => y.foreach { b =>
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@ -47,6 +49,7 @@ object AddressDecoder
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output
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}
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}
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// A simpler version that works for a Seq[Int]
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def apply(keys: Seq[Int]): Int = {
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