riscv/rocket-chip
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Add L2 TLB option

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This commit is contained in:
Andrew Waterman
2017-07-05 23:53:52 -07:00
parent 438abc76d2
commit 90a7d6a343
6 changed files with 73 additions and 6 deletions
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src/main/scala/rocket/NBDcache.scala
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@ -708,6 +708,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
dtlb.io.req.bits.sfence.valid := s1_sfence
dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
dtlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)
dtlb.io.req.bits.sfence.bits.addr := s1_req.addr
dtlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data.data
dtlb.io.req.bits.passthrough := s1_req.phys
dtlb.io.req.bits.vaddr := s1_req.addr