From 9044a4a4b7a78598a51972b0b29c23e9c7ea4a1e Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 27 Apr 2016 00:15:00 -0700
Subject: [PATCH] Replace NastiROM with ROMSlave, which uses TileLink

I'm not wedded to the name.
---
 uncore/src/main/scala/NastiROM.scala | 30 --------------------------
 uncore/src/main/scala/rom.scala      | 32 ++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 30 deletions(-)
 delete mode 100644 uncore/src/main/scala/NastiROM.scala
 create mode 100644 uncore/src/main/scala/rom.scala

diff --git a/uncore/src/main/scala/NastiROM.scala b/uncore/src/main/scala/NastiROM.scala
deleted file mode 100644
index 2c68340f..00000000
--- a/uncore/src/main/scala/NastiROM.scala
+++ /dev/null
@@ -1,30 +0,0 @@
-package uncore
-
-import Chisel._
-import junctions._
-import cde.{Parameters, Field}
-
-class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module {
-  val io = new NastiIO().flip
-  val ar = Queue(io.ar, 1)
-
-  // This assumes ROMs are in read-only parts of the address map.
-  // Reuse b_queue code from NastiErrorSlave if this assumption is bad.
-  when (ar.valid) { assert(ar.bits.len === UInt(0), "Can't burst-read from NastiROM") }
-  assert(!(io.aw.valid || io.w.valid), "Can't write to NastiROM")
-  io.aw.ready := Bool(false)
-  io.w.ready := Bool(false)
-  io.b.valid := Bool(false)
-
-  val byteWidth = io.r.bits.nastiXDataBits / 8
-  val rows = (contents.size + byteWidth - 1)/byteWidth + 1
-  val rom = Vec.tabulate(rows) { i =>
-    val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
-    UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
-  }
-  val rdata_word = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth)))
-  val rdata = new LoadGen(Cat(UInt(1), ar.bits.size), ar.bits.addr, rdata_word, Bool(false), byteWidth).data
-
-  io.r <> ar
-  io.r.bits := NastiReadDataChannel(ar.bits.id, rdata)
-}
diff --git a/uncore/src/main/scala/rom.scala b/uncore/src/main/scala/rom.scala
new file mode 100644
index 00000000..4e27db8c
--- /dev/null
+++ b/uncore/src/main/scala/rom.scala
@@ -0,0 +1,32 @@
+package uncore
+
+import Chisel._
+import junctions._
+import cde.{Parameters, Field}
+
+class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
+    with HasTileLinkParameters
+    with HasAddrMapParameters {
+  val io = new ClientUncachedTileLinkIO().flip
+
+  val acq = Queue(io.acquire, 1)
+  assert(!acq.valid || acq.bits.a_type === Acquire.getType, "unsupported ROMSlave operation")
+
+  val byteWidth = tlDataBits / 8
+  val rows = (contents.size + byteWidth - 1)/byteWidth + 1
+  val rom = Vec.tabulate(rows) { i =>
+    val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
+    UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
+  }
+  val rdata = rom(if (rows == 1) UInt(0) else acq.bits.full_addr()(log2Up(contents.size)-1,log2Up(byteWidth)))
+
+  io.grant.valid := acq.valid
+  acq.ready := io.grant.ready
+  io.grant.bits := Grant(
+    is_builtin_type = Bool(true),
+    g_type = acq.bits.getBuiltInGrantType(),
+    client_xact_id = acq.bits.client_xact_id,
+    manager_xact_id = UInt(0),
+    addr_beat = UInt(0),
+    data = rdata)
+}